Hardware accelerator test harness generation
System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.
1. A method of generating a test harness for a hardware accelerator comprising:
accessing a template simulation script corresponding to the hardware accelerator, the hardware accelerator including a plurality of inputs, a clock input, and a plurality of outputs;
determining a number of clock cycles required to complete execution of the hardware accelerator;
adding a first set of instructions to the simulation script to provide input parameters to the plurality of inputs during a test of the hardware accelerator;
adding a second set of instructions to the simulation script to provide clock inputs for the determined number of clock cycles required to complete execution of the hardware accelerator to the clock input during the test of the hardware accelerator;
adding a third set of instructions to the simulation script to access one or more output values from the plurality of outputs during the test of the hardware accelerator; and
accessing a waveform template script corresponding to the hardware accelerator, the waveform template script, when executed, configured to display the input parameters, the clock inputs, and the accessed output values.
2. The method of claim 1 , wherein the input parameters comprise initial values for the test of the hardware accelerator.
3. The method of claim 2 , wherein the initial values are chosen randomly, deterministically, or based on a design of the hardware accelerator.
4. The method of claim 1 , wherein the waveform template script is configured to display signals corresponding to ports of a highest hierarchical level of the hardware accelerator.
5. The method of claim 1 , wherein the input parameters provided by the first set of instructions comprise input parameters configured to simulate a request, from a host processor, for a performance of the a function of the hardware accelerator.
6. The method of claim 5 , wherein the accelerator is configured to:
perform the function based on the input parameters to generate the one or more output values, and
push the one or more output values to the plurality of outputs.
7. A computer program stored on a non-transitory computer-readable media and including instructions for generating a test harness for a hardware accelerator that, when executed by a processor, perform steps comprising:
accessing a template simulation script corresponding to the hardware accelerator, the hardware accelerator including a plurality of inputs, a clock input, and a plurality of outputs;
determining a number of clock cycles required to complete execution of the hardware accelerator;
adding a first set of instructions to the simulation script to provide input parameters to the plurality of inputs during a test of the hardware accelerator;
adding a second set of instructions to the simulation script to provide clock inputs for the determined number of clock cycles required to complete execution of the hardware accelerator to the clock input during the test of the hardware accelerator;
adding a third set of instructions to the simulation script to access one or more output values from the plurality of outputs during the test of the hardware accelerator; and
accessing a waveform template script corresponding to the hardware accelerator, the waveform template script, when executed, configured to display the input parameters, the clock inputs, and the accessed output values.
8. The computer program of claim 7 , wherein the input parameters comprise initial values for the test of the hardware accelerator.
9. The computer program of claim 8 , wherein the initial values are chosen randomly, deterministically, or based on a design of the hardware accelerator.
10. The computer program of claim 7 , wherein the waveform template script is configured to display signals corresponding to ports of a highest hierarchical level of the hardware accelerator.
11. The computer program of claim 7 , wherein the input parameters provided by the first set of instructions comprise input parameters configured to simulate a request, from a host processor, for a performance of a function of the hardware accelerator.
12. The computer program of claim 11 , wherein the accelerator is configured to:
perform the function based on the input parameters to generate the one or more output values, and
push the one or more output values to the plurality of outputs.
13. A system for generating a test harness for a hardware accelerator comprising:
a non-transitory computer-readable storage medium storing instructions that, when executed, perform steps comprising:
accessing a template simulation script corresponding to the hardware accelerator, the hardware accelerator including a plurality of inputs, a clock input, and a plurality of outputs;
determining a number of clock cycles required to complete execution of the hardware accelerator;
adding a first set of instructions to the simulation script to provide input parameters to the plurality of inputs during a test of the hardware accelerator;
adding a second set of instructions to the simulation script to provide clock inputs for the determined number of clock cycles required to complete execution of the hardware accelerator to the clock input during the test of the hardware accelerator;
adding a third set of instructions to the simulation script to access one or more output values from the plurality of outputs during the test of the hardware accelerator; and
accessing a waveform template script corresponding to the hardware accelerator, the waveform template script, when executed, configured to display the input parameters, the clock inputs, and the accessed output values; and
a processor configured to execute the instructions.
14. The system of claim 13 , wherein the input parameters comprise initial values for the test of the hardware accelerator.
15. The system of claim 14 , wherein the initial values are chosen randomly, deterministically, or based on a design of the hardware accelerator.
16. The system of claim 13 , wherein the waveform template script is configured to display signals corresponding to ports of a highest hierarchical level of the hardware accelerator.
17. The system of claim 13 , wherein the input parameters provided by the first set of instructions comprise input parameters configured to simulate a request, from a host processor, for a performance of a function of the hardware accelerator.
18. The system of claim 17 , wherein the accelerator is configured to:
perform the/function based on the input parameters to generate the one or more output values, and
push the one or more output values to the plurality of outputs.