Data reception chip
A data reception chip coupled to an external memory including a first input-output pin configured to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and to compare the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage. The voltage generation module includes a first resistor and a second resistor. The second resistor is connected to the first resistor in series. The first and second resistors divide a first operation voltage to generate the first reference voltage.
1. A data reception chip coupled to an external memory comprising a first input-output pin configured to output first data, comprising:
a comparison module coupled to the first input-output pin to receive the first data and comparing the first data with a first reference voltage to identify the value of the first data; and
a voltage generation module coupled to the comparison module, configured to generate the first reference voltage and comprising:
a first resistor; and
a second resistor connected to the first resistor in series, wherein the first and second resistors divide a first operation voltage to generate the first reference voltage.
2. The data reception chip as claimed in claim 1 , wherein the data reception chip accesses the external memory according to the first operation voltage and a second operation voltage.
3. The data reception chip as claimed in claim 2 , wherein the first resistor is connected to the second resistor in series between the first and second operation voltages.
4. The data reception chip as claimed in claim 2 , further comprising:
a capacitor configured to filter the noise of the first operation voltage.
5. The data reception chip as claimed in claim 4 , wherein the capacitor is connected to the second resistor in parallel, and the second resistor receives the second operation voltage.
6. The data reception chip as claimed in claim 2 , further comprising:
a capacitor configured to filter the noise of the second operation voltage.
7. The data reception chip as claimed in claim 6 , wherein the capacitor is connected to the first resistor in parallel, and the first resistor receives the first operation voltage.
8. The data reception chip as claimed in claim 1 , further comprising:
a terminal resistor coupled between the comparison module and the first operation voltage, wherein the comparison module comprises a comparator comprising a first input terminal and a second input terminal, the first input terminal is coupled between the first input-output pin and the terminal resistor, and the second input terminal receives the first reference voltage.
9. The data reception chip as claimed in claim 1 , wherein the comparison module comprises:
a first comparator comprising a first input terminal and a second input terminal, wherein the first input terminal is coupled to the first input-output pin, and the second input terminal receives the first reference voltage; and
a second comparator comprising a third input terminal and a fourth input terminal, wherein the third input terminal is coupled to a second input-output pin of the external memory to receive second data, the fourth input-output terminal receives the first reference voltage, and the second comparator compares the second data with the first reference voltage to identify the value of the second data.
10. The data reception chip as claimed in claim 1 , wherein the comparison module comprises:
a first comparator comparing the first data with the first reference voltage to identify the value of the first data; and
a second comparator is coupled to a second input-output pin of the external memory to receive second data and comparing the second data with a second reference voltage to identify the value of the second data, wherein the voltage generation module further comprises a third resistor and a fourth resistor, and the third and fourth resistors divide the first operation voltage to generate the second reference voltage.