Semiconductor structure and process thereof
A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.
1. A semiconductor structure, comprising:
at least a fin-shaped structure located on a bottom substrate;
a gate covering the fin-shaped structure;
a source/drain region located in the fin-shaped structure next to the gate;
an interdielectric layer covering the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region;
an epitaxial structure only located in each of the contact holes, directly contacting and only located on the source/drain region, wherein the band gap of the epitaxial structure is smaller than the band gap of the source/drain region;
a silicide located on the epitaxial structure in each of the contact holes, wherein the epitaxial structure in each of the contact holes is located between the silicide and the source/drain region;
a metal plug located on the silicide in each of the contact holes; and
a dielectric layer covering the interdielectric layer and the gate, wherein a top surface of the gate is on a same level as a top surface of the interdielectric layer and the dielectric layer has a gate contact hole exposing at least a part of the gate.
2. The semiconductor structure according to claim 1 , wherein the gate comprises a polysilicon gate or a metal gate.
3. The semiconductor structure according to claim 1 , further comprising a contact etch stop layer located between the interdielectric layer and the fin-shaped structure.
4. The semiconductor structure according to claim 1 , wherein the epitaxial structure comprises a strained epitaxial silicon.