Semiconductor device with high electron mobility transistor (HEMT) having source field plate

1. A semiconductor device, comprising:

a Group III nitride semiconductor lamination structure including a hetero-junction;

an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure;

a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion;

a gate electrode formed on the gate insulating film in the gate opening portion;

a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and

a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.

2. The semiconductor device of claim 1 , further comprising:

an insulating sidewall disposed between the gate insulating film and the side portion of the gate opening portion.

3. The semiconductor device of claim 2 , wherein the sidewall includes at least one kind of material selected from a group consisting of SiO 2 , SiN and SiON.

4. The semiconductor device of claim 1 , wherein a distance L GF between the gate electrode and the conductive layer is 1 μor less.

5. The semiconductor device of claim 1 , wherein a length L FP of the conductive layer and a distance L GD between the gate electrode and the drain electrode satisfy an inequality of L FP <⅓L GD .

6. The semiconductor device of claim 1 , wherein the gate insulating film includes, as a constituent element, at least one kind of material selected from a group consisting of Si, Al and Hf.

7. The semiconductor device of claim 1 , wherein the gate electrode includes a metal electrode.

8. The semiconductor device of claim 1 , wherein the gate electrode includes an overlap portion formed on the gate insulating film at a peripheral edge of the gate opening portion.

9. The semiconductor device of claim 1 , wherein the Group III nitride semiconductor lamination structure includes an active region including an element structure formed by sandwiching the gate electrode with the source electrode and the drain electrode and a non-active region other than the active region,

each of the source electrode and the conductive layer includes an extension portion extending to the non-active region, and

the extension portion of the source electrode and the extension portion of the conductive layer are connected to each other.

10. The semiconductor device of claim 1 , wherein the Group III nitride semiconductor lamination structure includes a first semiconductor layer forming the hetero-junction and a second semiconductor layer formed on the first semiconductor layer, and

the second semiconductor layer includes an oxide film selectively formed in the bottom portion of the gate opening portion by oxidizing the second semiconductor layer.

11. The semiconductor device of claim 1 , wherein the Group III nitride semiconductor lamination structure includes a first semiconductor layer forming the hetero-junction and a second semiconductor layer formed on the first semiconductor layer, and

the second semiconductor layer is selectively etched only in the bottom portion of the gate opening portion.

12. The semiconductor device of claim 1 , further comprising:

an underlying layer that is disposed between the conductive layer and the Group III nitride semiconductor lamination structure and extends to formation regions of the source electrode and the drain electrode,

wherein at least one of the source electrode and the drain electrode includes an ohmic electrode disposed in the underlying layer and a pad electrode in the insulating layer formed on the ohmic electrode.

13. The semiconductor device of claim 12 , wherein the underlying layer has a thickness of 5 nm to 200 nm and the insulating layer has a thickness of 1.5 μm to 2 μm.

14. The semiconductor device of claim 1 , further comprising:

a second conductive layer embedded in the insulating layer between the gate electrode and the source electrode, the second conductive layer insulated from the gate electrode by the gate insulating film and also insulated from the source electrode.

15. A semiconductor device, comprising:

a Group III nitride semiconductor lamination structure including a hetero-junction;

an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure;

a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion;

a gate electrode formed on the gate insulating film in the gate opening portion;

a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and

a source field plate embedded in the insulating layer to partially form the side portion of the gate opening portion between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the source field plate electrically connected to the source electrode.

16. The semiconductor device of claim 15 , further comprising:

an insulating sidewall formed in the side portion of the gate opening portion to make contact with the source field plate,

wherein the gate insulating film is formed to cover the sidewall.