Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

1. A computer system for implementing resistive defect performance mitigation for integrated circuits comprising:

a processor;

a test generator;

a resistive defect performance mitigation control;

said processor using said test generator and said resistive defect performance mitigation control to implement resistive defect performance mitigation for a sample integrated circuits;

said processor using said test generator for identifying resistive defects;

said processor using said resistive defect performance mitigation control for performing a first self heating repair process for repairing resistive defects;

said processor using said test generator for performing testing to identify a mitigated resistive defect and a functional integrated circuit; and

said processor using said resistive defect performance mitigation control responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, for performing a second repair process, and repeating testing to identify a mitigated resistive defect and a functional integrated circuit.

2. The system as recited in claim 1 includes control code stored on a computer readable medium, and wherein said processor uses said control code for implementing resistive defect performance mitigation for integrated circuits.

3. The system as recited in claim 1 wherein the first self heating repair process includes repeatedly switching a signal to a circuit path containing the resistive defect at a selected frequency and a selected voltage for a set duration.

4. The system as recited in claim 3 wherein said selected frequency is approximately equal or slightly above a maximum frequency at which the integrated circuit functions, and said set duration equals a set number of microseconds allowing millions of switches.

5. The system as recited in claim 3 wherein the repeated switching is provided at a set elevated voltage to enhance localized heating and stressing of any residual dielectric films in the connecting area.

6. The system as recited in claim 1 wherein repairing resistive defects includes one or more of repairing resistive connections in a contact, a via, and a high resistance defect present in an internally embedded interconnect.

7. The system as recited in claim 1 wherein performing testing to identify a mitigated resistive defect and a functional integrated circuit includes said processor using said resistive defect performance mitigation control, applying an appropriate voltage for use of the integrated circuit to a defect node, and testing to identify a mitigated resistive defect and a functional integrated circuit.

8. The system as recited in claim 1 wherein said second repair process includes said processor using said resistive defect performance mitigation control, using a laser to enhance the local heating.

9. The system as recited in claim 1 wherein said second repair process includes said processor using said resistive defect performance mitigation control, providing incremental voltage steps to a defect node and repeating until a mitigated resistive defect is identified or a maximum voltage is reached.

10. The system as recited in claim 1 includes said processor using said resistive defect performance mitigation control, identifying a successful repair, responsive to identifying a resistive defect being mitigated and a functional integrated circuit being identified.

11. The system as recited in claim 1 includes said processor using said resistive defect performance mitigation control, discarding the integrated circuit, responsive to a functional integrated circuit not being identified.