IP Library Granted Patent US 9,754,909
Granted Patent B2
US 9,754,909 · App. 14/944,054 · Granted Sep 5, 2017

Copper structures with intermetallic coating for integrated circuit chips

Inventor: Hunt Hang Jiang (Saratoga, CA)
Assignee: Monolithic Power Systems, Inc.
H01L24/13H01L24/11H01L2224/03462H01L2224/03464H01L2224/03825H01L2224/11848H01L2224/80801H01L2224/80815H01L2924/014H01L2924/0105H01L2924/01013H01L2924/01029
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Quick Facts
Patent No.
US 9,754,909
App. No.
14/944,054
Granted
Sep 5, 2017
Kind
B2
Abstract

An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

Claims (14)

1. A method of manufacturing an integrated circuit (IC) chip, the method comprising:

forming a copper seed layer over a substrate, the copper seed layer being formed to electrically connect to a metal pad that electrically connects to an integrated circuit in the substrate;

electroplating a first copper layer on the copper seed layer;

electroplating a second copper layer on the first copper layer;

electroplating solder on the second copper layer;

electroless plating a coating of tin on a surface of the first copper layer, the second copper layer, and the solder; and

heating the coating of tin to form a tin-copper intermetallic coating on the surface of the first copper layer and the second copper layer.

2. The method of claim 1 , wherein the metal pad comprises an input/output pad of the IC chip.

3. The method of claim 2 , wherein the second copper layer comprises a redistribution layer that electrically connects to the input/output pad of the IC chip.

4. The method of claim 3 , wherein the second copper layer comprises a copper pillar that electrically connects to the redistribution layer.

5. The method of claim 1 , wherein the copper seed layer is formed on a passivation layer.

6. The method of claim 5 , wherein the passivation layer comprises a plurality of micro-vias formed on the metal pad.

7. The method of claim 5 , wherein the passivation layer comprises silicon nitride.

8. The method of claim 1 , wherein heating the coating of tin comprises: reflowing the solder in a reflow process to form a solder bump.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2015
From: JIANG, HUNT HANG
To: MONOLITHIC POWER SYSTEMS, INC.
Reel/Frame 037210/0288 →
Continuity (2)
Provisional Application 62166567 · May 26, 2015
Related Publication 20160351520A1 · Dec 1, 2016