Semiconductor device having nanowire
A semiconductor device is provided as follows. A first nanowire is disposed on a substrate. The first nanowire is extended in a first direction and spaced apart from the substrate. A gate electrode surrounds a periphery of the first nanowire. The gate electrode is extended in a second direction intersecting the first direction. A gate spacer is formed on a sidewall of the gate electrode. The gate spacer includes an inner sidewall and an outer sidewall facing each other. The inner sidewall of the gate spacer faces the sidewall of the gate electrode. An end portion of the first nanowire is protruded from the outer sidewall of the gate spacer. A source/drain epitaxial layer is disposed on at least one side of the gate electrode. The source/drain is connected to the protruded end portion of the first nanowire.
1. A semiconductor device, comprising:
a first nanowire disposed on a substrate,
wherein the first nanowire is extended in a first direction and spaced apart from the substrate;
a gate electrode surrounding a periphery of the first nanowire, wherein the gate electrode is extended in a second direction intersecting the first direction;
a gate spacer formed on a sidewall of the gate electrode,
the gate spacer comprising an inner sidewall and an outer sidewall facing each other,
wherein the inner sidewall of the gate spacer faces the sidewall of the gate electrode and an end portion of the first nanowire is protruded from the outer sidewall of the gate spacer; and
a source/drain epitaxial layer disposed on at least one side of the gate electrode, wherein the source/drain epitaxial layer is connected to the end portion of the first nanowire,
wherein the gate spacer comprises an inner spacer and an outer spacer surrounding the inner spacer in a cross-section taken along the second direction,
wherein the inner spacer is located between the substrate and the first nanowire,
wherein the inner spacer includes a sidewall extending in the first direction,
wherein the outer spacer covers the sidewall of the inner spacer and is in contact with the sidewall of the inner spacer, and
wherein the first nanowire is in contact with the outer spacer and the inner spacer.
2. The semiconductor device of claim 1 ,
wherein the first nanowire is disposed between the outer spacer and the inner spacer in the cross-section.
3. The semiconductor device of claim 1 ,
wherein the inner spacer and the outer spacer have different dielectric constants from each other.
4. The semiconductor device of claim 3 ,
wherein the dielectric constant of the inner spacer is smaller than that of the outer spacer.
5. The semiconductor device of claim 1 ,
wherein a top surface of the first nanowire is in contact with the outer spacer, and
a bottom surface of the first nanowire is in contact with the inner spacer.
6. The semiconductor device of claim 1 ,
wherein thicknesses of the inner spacer and the outer spacer are different from each other.
7. The semiconductor device of claim 6 ,
wherein the thickness of the inner spacer is greater than the thickness of the outer spacer.
8. The semiconductor device of claim 1 , further comprising:
a second nanowire disposed on the substrate and extended in the first direction, wherein the first nanowire is interposed between the second nanowire and the substrate, and a periphery of the second nanowire is surrounded by the gate electrode.
9. The semiconductor device of claim 8 ,
wherein the gate spacer comprises an inner spacer and an outer spacer surrounding the inner spacer in a cross-section taken along the second direction, and
wherein the inner spacer is located between the substrate and the first nanowire, and between the first nanowire and the second nanowire in the cross-section.
10. The semiconductor device of claim 1 ,
wherein the outer sidewall of the gate spacer includes a sidewall of the inner spacer and a sidewall of the outer spacer, and
wherein the sidewall of the inner spacer and the sidewall of the outer spacer are aligned to each other to form the outer sidewall of the gate spacer.
11. A semiconductor device, comprising:
a gate electrode disposed on a substrate and extended in a first direction;
an inner spacer formed on the substrate and a first portion of a sidewall of the gate electrode;
an outer spacer formed on a second portion of the sidewall of the gate electrode,
wherein the second portion of the sidewall of the gate electrode surrounds the first portion of the sidewall of the gate electrode;
a first nanowire disposed on the substrate,
wherein the first nanowire is extended in a second direction which is different from the first direction and an end portion of the first nanowire is protruded from the inner spacer and the outer spacer; and
a source/drain connected with the end portion of the first nanowire,
wherein the inner spacer is located between the substrate and the first nanowire,
wherein the inner spacer includes a sidewall extending in the first direction,
wherein the outer spacer covers the sidewall of the inner spacer and is in contact with the sidewall of the inner spacer, and
wherein the first nanowire is in contact with the outer spacer and the inner spacer.
12. The semiconductor device of claim 11 ,
wherein the inner spacer and the outer spacer have different dielectric constants from each other.
13. The semiconductor device of claim 11 ,
wherein thicknesses of the inner spacer and the outer spacer are different from each other.
14. The semiconductor device of claim 11 ,
wherein the first nanowire passes through the gate electrode in the second direction.
15. The semiconductor device of claim 11 , further comprising:
a second nanowire disposed on the substrate,
wherein the first nanowire is interposed between the second nanowire and the substrate, and
wherein the second nanowire passes through the gate electrode in the second direction.
16. A semiconductor device, comprising:
a plurality of nanowires disposed on a substrate,
wherein each of the plurality of nanowires is extended in a first direction and spaced apart from the substrate;
a gate electrode surrounding a periphery of each of the plurality of nanowires,
wherein the gate electrode is extended in a second direction intersecting the first direction;
a gate spacer formed on a sidewall of the gate electrode,
the gate spacer comprising an inner sidewall and an outer sidewall facing each other,
wherein the inner sidewall of the gate spacer faces the sidewall of the gate electrode and an end portion of each of the plurality of nanowires is protruded from the outer sidewall of the gate spacer; and
a source/drain epitaxial layer disposed on at least one side of the gate electrode,
wherein the source/drain epitaxial layer is connected to the end portion of each of the plurality of nanowires,
wherein the gate spacer comprises an inner spacer and an outer spacer surrounding the inner spacer in a cross-section taken along the second direction,
wherein the inner spacer is located between the substrate and each of the plurality of nanowires,
wherein the inner spacer includes a sidewall extending in the first direction,
wherein the outer spacer covers the sidewall of the inner spacer and is in contact with the sidewall of the inner spacer, and
wherein each of the plurality of nanowires is in contact with the outer spacer and the inner spacer.
17. The semiconductor device of claim 16 ,
wherein the plurality of nanowires comprises a first nanowire spaced apart a first distance from the substrate and a second nanowire spaced apart a second distance that greater than the first distance from the substrate.
18. The semiconductor device of claim 17 ,
wherein the first nanowire and the second nanowire are overlapped vertically.