Three level neutral point clamped converter with improved voltage balancing
An NPC converter is controlled by estimating current flow during the short vector periods of a space vector modulation drive signal. The current estimation is used to close a first order inner current regulator loop that steers current to either the upper capacitor or the lower capacitor of a DC link. An outer voltage regulator measures the voltage imbalance across the capacitors and drives the inner current loop. By managing the associated duty cycle of each vector a bias current is formed that balances the capacitor voltages.
1. A converter, comprising:
a neutral point clamped (NPC) converter module comprising:
a plurality of phase legs, each phase leg comprising a plurality of switches coupled in series with one another between a first node and a second node, each phase leg further comprising an AC node positioned between two adjacent switches;
a current sensor coupled to each AC node and configured to measure an amount of current flowing into, or out of, each respective AC node; and
a controller, coupled to the NPC converter module and the current sensor, configured to:
generate a space vector pulse width modulated (SVPWM) signal to control a respective on/off condition of each of the plurality of switches as a function of:
a short vector current signal generated as a function of a value of the current sensed at the respective AC nodes during short vector periods of the SVPWM signal; and
a respective voltage differential between a first voltage on the first node and a second voltage on the second node, each with respect to a third node.
2. The converter of claim 1 , wherein the controller is further configured to:
adjust a modulation index signal as a function of the short vector current signal.
3. The converter of claim 1 , wherein the controller further comprises:
a proportional integrator (PI) current regulator configured to generate a voltage command signal as a function of the short vector current signal; and
a space vector PWM modulator configured to receive the voltage command signal and generate the SVPWM signal as a function thereof.
4. The converter of claim 3 , wherein the controller further comprises:
a proportional integrator (PI) voltage regulator configured to output a current regulator command signal; and
a difference module configured to output a difference value representing a difference between the short vector current signal and the current regulator command signal,
wherein the PI current regulator is further configured to generate the voltage command signal as a function of the difference value.
5. The converter of claim 1 , wherein the controller is further configured to generate each cycle of the SVPWM signal to start and end with a positive short vector portion and to include two negative short vector portions of equal duration in the middle of the cycle.
6. The converter of claim 5 , wherein the controller is further configured to adjust a time duration of one or more of the positive and negative short vector portions of the SVPWM signal as a function of the short vector current signal.
7. A method of operating a multi-level neutral point clamped converter comprising:
measuring AC current flowing in the converter;
generating a short vector current signal representing a component of the measured AC current during a short vector period of a space vector pulse width modulated (SVPWM) driving signal;
measuring a voltage difference between respective voltages on each of two capacitors in a DC link portion of the converter; and
modifying the SVPWM driving signal as a function of the generated short vector current signal and the measured voltage difference.
8. The method of claim 7 , further comprising:
adjusting a modulation index signal as a function of the short vector current signal.
9. The method of claim 7 , further comprising:
generating a current regulator command signal as a function of the short vector current signal; and
and generating the SVPWM signal as a function of the current regulator command signal.
10. The method of claim 9 , further comprising:
generating a difference value representing a difference between the short vector current signal and the current regulator command signal; and
generating the voltage command signal as a function of the difference value.
11. The method of claim 7 , further comprising generating each cycle of the SVPWM signal to start and end with a positive short vector portion and to include two negative short vector portions of equal duration in the middle of the cycle.
12. The method of claim 11 , further comprising adjusting adjust a time duration of one or more of the positive and negative short vector portions of the SVPWM signal as a function of the short vector current signal.
13. A non-transitory computer readable media comprising instructions stored thereon that, when executed by a processing apparatus, cause the processing apparatus to implement a method of operating a multi-level neutral point clamped converter, the method comprising:
measuring AC current flowing in the converter;
generating a short vector current signal representing a component of the measured AC current during a short vector period of a space vector pulse width modulated (SVPWM) driving signal;
measuring a voltage difference between respective voltages on each of two capacitors in a DC link portion of the converter; and
modifying the SVPWM driving signal as a function of the generated short vector current signal and the measured voltage difference.
14. The computer readable media of claim 13 , the method further comprising:
adjusting a modulation index signal as a function of the short vector current signal.
15. The computer readable media of claim 13 , the method further comprising:
generating a current regulator command signal as a function of the short vector current signal; and
and generating the SVPWM signal as a function of the current regulator command signal.
16. The computer readable media of claim 15 , the method further comprising:
generating a difference value representing a difference between the short vector current signal and the current regulator command signal; and
generating the voltage command signal as a function of the difference value.
17. The computer readable media of claim 13 , the method further comprising generating each cycle of the SVPWM signal to start and end with a positive short vector portion and to include two negative short vector portions of equal duration in the middle of the cycle.
18. The computer readable media of claim 17 , the method further comprising adjusting adjust a time duration of one or more of the positive and negative short vector portions of the SVPWM signal as a function of the short vector current signal.