IP Library Granted Patent US 9,759,966
Granted Patent B2
US 9,759,966 · App. 15/253,095 · Granted Sep 12, 2017

Array substrate and method of manufacturing the same, and display device

Inventors: Pengju Zhang (Beijing, CN); Xin Li (Washington, DC); Bin Li (Beijing, CN); Detao Zhao (Beijing, CN); Xuchen Yuan (Beijing, CN)
Assignees: BOE Technology Group Co., Ltd.; Beijing BOE Optoelectronics Technology Co., Ltd.
G02F1/136204G02F1/1368G02F1/134309G02F1/136286H01L27/0248H01L27/3272G02F1/1341G02F1/13439G02F1/133514G02F1/136227G02F2201/122G02F2201/123H01L2227/323
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Quick Facts
Patent No.
US 9,759,966
App. No.
15/253,095
Granted
Sep 12, 2017
Kind
B2
Abstract

An array substrate and a method of manufacturing the same, and a display device are disclosed. The array substrate includes a base substrate; a pixel electrode, a thin film transistor, a gate line and a data line that are provided on the base substrate; and an electrostatic shielding layer provided on the base substrate. The electrostatic shielding layer is configured for electrostatic protection during production of the array substrate.

Claims (19)

1. An array substrate, comprising:

a base substrate,

a pixel electrode, a thin film transistor, a gate line and a data line that are provided on the base substrate, and

an electrostatic shielding layer provided on the base substrate, wherein the electrostatic shielding layer is configured for electrostatic protection during production of the array substrate,

wherein the electrostatic shielding layer comprises a plurality of longitudinal portions and a plurality of transverse portions, and the plurality of longitudinal portions and the plurality of transverse portions intersect to form a grid pattern.

2. The array substrate according to claim 1 , further comprising an insulation layer that is provided on a side of the electrostatic shielding layer away from the base substrate, wherein the thin film transistor, the gate line and the data line are all provided on a side of the insulation layer away from the electrostatic shielding layer.

3. The array substrate according to claim 1 , wherein the array substrate comprises a plurality of gate lines and a plurality of data lines, a projection of the plurality of longitudinal portions on the array substrate is provided within a projection of the data lines on the array substrate, and a projection of the plurality of transverse portions on the array substrate is provided within a projection of the gate lines on the array substrate.

4. The array substrate according to claim 1 , wherein the electrostatic shielding layer and the pixel electrode layer are disposed in a same layer and are made of a same material.

5. The array substrate according to claim 1 , further comprising a ground circuit, wherein the electrostatic shielding layer is electrically connected to the ground circuit.

6. A display device, comprising the array substrate according to claim 1 .

7. The display device according to claim 6 , wherein the display device is a liquid crystal display device, an organic light-emitting diode display device, or an e-ink display device.

8. A method of manufacturing an array substrate, comprising:

forming a pixel electrode, a thin film transistor, a gate line and a data line on a base substrate, and

forming an electrostatic shielding layer on the base substrate, the electrostatic shielding layer being configured for electrostatic protection during production of the array substrate,

wherein the electrostatic shielding layer comprises a plurality of longitudinal portions and a plurality of transverse portions, and the plurality of longitudinal portions and the plurality of transverse portions intersect to form a grid pattern.

9. The method of manufacturing an array substrate according to claim 8 , wherein forming of the thin film transistor, the gate line and the data line is conducted after forming of the electrostatic shielding layer; and the method further comprises:

forming an insulation layer on the electrostatic shielding layer after forming of the electrostatic shielding layer and prior to forming of the thin film transistor, the gate line and the data line.

10. The method of manufacturing an array substrate according to claim 8 , wherein a plurality of gate lines and a plurality of data lines are formed, a projection of the plurality of longitudinal portions on the array substrate is provided within a projection of the data lines on the array substrate, and a projection of the plurality of transverse portions on the array substrate is provided within a projection of the gate lines on the array substrate.

11. The method of manufacturing an array substrate according to claim 8 , wherein the electrostatic shielding layer and the pixel electrode are simultaneously formed in a patterning process.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE FIRST RECEIVING PARTY'S DATA PREVIOUSLY RECORDED ON REEL 039635 FRAME 0958. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 21, 2016
From: ZHANG, PENGJU; LI, XIN; LI, BIN; ZHAO, DETAO; YUAN, XUCHEN
To: BOE TECHNOLOGY GROUP CO., LTD.; BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 040095/0291 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2016
From: ZHANG, PENGJU; LI, XIN; LI, BIN; ZHAO, DETAO; YUAN, XUCHEN
To: BOE TECHNOLOGY GROUP CO., LTD.; BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 039635/0958 →
Priority Claims (1)
CN 2016 1 0007356 · Jan 6, 2016 · national
Continuity (1)
Related Publication 20170192319A1 · Jul 6, 2017