Synchronization of a data signal
A method for synchronizing a data signal in a bus environment is suggested, the method may include providing multiple clock phases based on a reference oscillator; determining a phase out of the multiple clock phases for a transition of a data signal; and synchronizing the data signal based on the phase determined.
1. A method for synchronizing a data signal in a bus environment, the method comprising:
providing multiple clock phases based on a reference oscillator, wherein a frequency of the references oscillator is 20 MHz or below;
selecting a phase from the multiple clock phases for a transition of a data signal as a sampling phase; and
synchronizing the data signal based on the sampling phase, wherein the data signal is a received message on a controller area network (CAN) bus.
2. The method according to claim 1 , further comprising:
providing multiple clock phases based on a reference oscillator via a delay unit.
3. The method according to claim 2 , wherein the delay unit is a delay-locked loop unit.
4. The method according to claim 1 , further comprising:
providing equidistant multiple clock phases based on a reference oscillator via a delay-locked loop unit.
5. The method according to claim 1 , wherein the transition is a recessive-to-dominant transition.
6. The method according to claim 1 , further comprising:
determining a wake-up signal based on the synchronized data signal.
7. The method according to claim 1 , further comprising:
determining the phase from the multiple clock phases for the transition of the data signal based on at least one of a predefined offset and an alignment.
8. The method according to claim 1 , further comprising:
determining a synchronization phase out of the multiple clock phases for the transition of the data signal;
determining a sampling point based on at least one of a predefined offset and an alignment; and
selecting the phase out of the multiple clock phases based on the sampling point.
9. The method according to claim 1 , wherein the multiple clock phases have a same frequencies.
10. The method according to claim 1 , wherein the multiple clock phases have a same frequency as a frequency of the reference oscillator.
11. The method according to claim 1 , wherein the multiple clock phases have a lower frequency as a frequency of the reference oscillator.
12. The method according to claim 1 , wherein a frequency of the reference oscillator is 5 MHz or below.
13. A device comprising a processing unit that is configured to
provide multiple clock phases based on a reference oscillator, wherein a frequency of the references oscillator is 20 MHz or below;
select a phase from the multiple clock phases for a transition of a data signal as a sampling phase; and
synchronize the data signal based on the sampling phase, wherein the data signal is a received message on a controller area network (CAN) bus.
14. The device according to claim 13 , wherein the device is a bus controller or part of a bus controller.
15. The device according to claim 13 , wherein the device is integrated on a single chip.
16. The device according to claim 13 , further comprising a delay-locked loop configured to provide the multiple clock phases.
17. A system comprising:
means for providing multiple clock phases based on a reference oscillator, wherein a frequency of the references oscillator is 20 MHz or below;
means for selecting a phase from the multiple clock phases for a transition of a data signal as a sampling phase; and
means for synchronizing the data signal based on the sampling phase, wherein the data signal is a received message on a controller area network (CAN) bus.