Strained channel field effect transistor
The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.
1. A semiconductor device comprising:
a substrate;
a first dielectric structure disposed on the substrate;
a second dielectric structure disposed on the substrate;
a fin structure disposed on the substrate between the first dielectric structure and the second dielectric structure, wherein the fin structure includes a first epitaxial layer disposed on the substrate and a second epitaxial layer disposed on the first epitaxial layer, wherein the fin structure has a curved interface with the first dielectric structure and a curved interface with the second dielectric structure, and wherein the fin structure has a varying width that is widest at the substrate;
a third epitaxial layer disposed on at least three sides of a portion of the fin structure extending above the first dielectric structure and the second dielectric structure, wherein the third epitaxial layer includes a compressively-strained material; and
a gate structure disposed on the third epitaxial layer, such that the third epitaxial layer extends continuously underneath the entire gate structure and a channel is defined in the third epitaxial layer, wherein the third epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component.
2. The semiconductor device of claim 1 , wherein the third epitaxial layer includes silicon-germanium (SiGe).
3. The semiconductor device of claim 1 , wherein the third epitaxial layer is different in composition from the fin structure.
4. The semiconductor device of claim 1 , wherein the fin structure comprises Si throughout.
5. The semiconductor device of claim 1 , wherein each of the first dielectric structure and the second dielectric structure is disposed on a top surface of the substrate, and wherein the fin structure extends from the top surface of the substrate to a height above the first dielectric structure and the second dielectric structure.
6. The semiconductor device of claim 1 , wherein the third epitaxial layer is disposed on substantially all of the fin structure that extends above the first dielectric structure and the second dielectric structure.
7. The semiconductor device of claim 1 , wherein the third epitaxial layer is disposed on substantially all surfaces of the second epitaxial layer that extend above the first dielectric structure and the second dielectric structure.