Resistive field structures for semiconductor devices and uses therof
The present disclosure relates to resistive field structures that provide improved electric field profiles when used with a semiconductor device. In particular, the resistive field structures provide a uniform electric field profile, thereby enhancing breakdown voltage and improving reliability. In example, the structure is a field cage that is configured to be resistive, in which the potential changes significantly over the distance of the cage. In another example, the structure is a resistive field plate. Using these resistive field structures, the characteristics of the electric field profile can be independently modulated from the physical parameters of the semiconductor device. Additional methods and architectures are described herein.
1. An apparatus comprising:
(i) a semiconductor device comprising a source, a gate, and a drain; and
(ii) a resistive field cage coupled to the semiconductor device, the resistive field cage comprising:
a resistive element, comprising a resistive material, electrically coupled between the source and the drain of the semiconductor device; and
a plurality of n field cage taps, n an integer at least 3 but not more than 20, disposed above the semiconductor device and between the source and the drain, wherein each of the n field cage taps is electrically coupled between a top surface of the semiconductor device and the resistive element;
wherein:
the plurality of n field cage taps comprises a first field cage tap located nearest the source followed by n−1 consecutive field cage taps disposed between the first field cage tap and the drain, an edge-to-edge distance d tap of at least 400 nm separating each of the n−1 consecutive field cage taps from a preceding field cage tap;
the semiconductor device further comprises a base substrate, a buffer layer disposed above the base substrate, a barrier layer disposed above the buffer layer, and a passivation layer disposed above the barrier layer, in which the buffer layer forms with the barrier layer a heterojunction configured to provide a channel region that accumulates a two-dimensional electron gas (2DEG);
the buffer layer has a composition comprising at least one substance selected from the group consisting of gallium nitride, gallium arsenide, indium nitride, indium phosphide, indium gallium nitrides, and aluminum indium gallium nitrides;
the passivation layer comprises one or more materials selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, zinc oxide, zirconium oxide, hafnium oxide, titanium oxide, carbon-doped silicon oxide, carbon-doped silicon nitride, and carbon-doped silicon oxynitride;
the plurality of n field cage taps lie directly on or within the passivation layer; and
beneath the plurality of n field cage taps, the passivation layer has a thickness h pass of at least 400 nm but not more than 700 nm.
2. The apparatus of claim 1 , wherein the resistive material comprises a p-type material, silicon, aluminum gallium nitride, tantalum nitride, and/or titanium nitride.
3. The apparatus of claim 1 , wherein the resistive element comprises a film of the resistive material patterned on an insulator layer.
4. The apparatus of claim 1 , wherein the resistive element comprises n resistors in series, and wherein each resistor is electrically coupled to one of the plurality of n field cage taps.
5. The apparatus of claim 1 , wherein the resistive element has a resistance ranging from about 1 GΩ to about 10 GΩ.
6. The apparatus of claim 1 , wherein dtap ranges from about 400 nm to about 500 nm.
7. The apparatus of claim 1 , wherein a length of each field cage tap Ltap, ranges from about 500 nm to about 1000 nm.
8. The apparatus of claim 1 , wherein the buffer layer comprises gallium nitride and the barrier layer comprises aluminum gallium nitride.
9. The apparatus of claim 1 , wherein the plurality of n field cage taps is coupled to a top surface of the passivation layer.
10. The apparatus of claim 1 , further comprising an insulator layer disposed beneath the passivation layer, and wherein the gate is disposed within the passivation layer and above the insulator layer.