Method and device for fast fourier transform

1. A Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT) method, comprising:

controlling an address calculating unit of a processor to convert a set of reversal-order or a set of natural-order addresses of FFT/IFFT data to a set of addresses in a radix-based numeral representation;

controlling the address calculating unit to calculate sequence numbers of a plurality of memory locations for buffering a set of data for a parallel calculation, by accumulating or subtracting ail digits of the set of addresses in the radix-based numeral representation and then performing a modulo operation on the accumulation or subtraction results, wherein the radix represents a length of short OFT sequence for the parallel calculation in a FFT/IFFT calculation;

controlling an interface unit of the processor to store the FFT/IFFT data simultaneously and respectively into corresponding memory locations indicated by the calculated sequence numbers; and

controlling an FFT/IFFT calculation unit of the processor to perform a FFT/IFFT calculation, comprising:

performing a short DFT sequence calculation, comprising:

retrieving corresponding data from the memory, inputting directly the corresponding data into a short DFT sequence calculator for calculation, modifying the calculated data with a modified twiddle factor, in-place storing the modified data back to the memory directly;

repeating the short DFT sequence calculation, until the whole FFT/IFFT calculation completes.

2. The method of claim 1 , wherein the calculated sequence numbers of the plurality of memory locations are cyclical shifts of data sequence numbers used in a short DFT sequence calculation.

3. The method of claim 1 , further comprising inputting each modified data for the short DFT sequence calculation directly into an input port corresponding to the FFT/IFFT calculation unit without reordering the data.

4. The method of claim 2 , wherein each digit of the set of addresses in the radix-based numeral representation of the data comprises a plurality of bits, wherein before calculating the sequence numbers of a plurality of the memory locations, the method further comprises:

converting each digit by performing XOR operation on two of the plurality of bits of each digit, wherein the calculated sequence numbers of the plurality of memory locations are a part of cyclical shifts of data sequence numbers used in one short DFT sequence calculation.

5. The method of claim 1 , wherein performing the short DFT sequence calculation further comprises:

modifying the data to be treated with the short DFT sequence calculation with a first modifying factor, wherein the first modifying factor is represented as exp[j×(B×n) r ×2pi/r], n=0, 1, 2 . . . r−1;

treating the modified sequence with a twiddle factor exp[(−j×(B i ×(B i−1 B i−2 . . . B 1 B 0 )×r^(s−i))×2pi/N)];

inputting the treated sequence into the short DFT sequence calculator for calculation;

modifying the data after DFT calculation with a second modifying factor, wherein the second modifying factor is represented as exp[j×(B×k) r ×2pi/r)+(−j×(B×B) r ×2pi/r)], wherein B=(ΣB s ) r , (s≠i−1), i represents a stage of FFT/IFFT calculation, the data have an address of B s−1 B s−2 B i . . . B 1 B 0 , and Bi=0, 1, 2 . . . r−1, r represents a radix of FFT calculation, each of B s−1 , B s−2 , B 1 , B 0 is a radix-based digit, and N represents a number of points of FFT/IFFT calculation.

6. The method of claim 1 , wherein performing the short DFT sequence calculation, further comprising:

modifying the data calculated by the short DFT sequence calculation with the modified twiddle factor, wherein the modified twiddle factor is represented as exp[(−j×(B i+1 ×(B i B i−1 . . . B i B 0 )×r^(s−i))×2pi/N)+(j×(B×k) r ×2pi/r)+(j×(C×n) r ×2pi/r)+(−j×(B×B) r ×2pi/r)], wherein B=(ΣB s ) r , (s≠i−1), C=ΣBs) r , (s≠i), i represents a stage of FFT/IFFT calculation, the data have an address of B S−1 B s−2 B i . . . B 1 B 0 , and Bi=0, 1, 2 . . . r−1, r represents a radix of FFT/IFFT calculation, each of B s−1 , B s−2 , B 1 , B 0 is a radix-based digit, and N represents a number of points of FFT/IFFT calculation.

7. The method of claim 1 , wherein a list between values of twiddle factors and index is stored in the memory, and the method further comprises obtaining an updated index by adding a higher R bits of the twiddle factor with a modified value, wherein the updated index corresponds to the modified twiddle factor, and the method further comprises:

modifying the data after DFT calculation with the modified twiddle factor, wherein R is represented as log 2(r), and r represents a radix of a FFT calculation.

8. The method of claim 1 , wherein the set of data comprises data to be computed in a first stage of FFT/IFFT calculation,

Weighing the data with an equation of exp(j×(C×n) r ×2pi/r), n=B 0 , C=(ΣB s ), (s≠0) during inputting, wherein the data have an address of B s−1 B s−2 B i . . . B 1 B 0 , and Bi=0, 1, 2 . . . r−1, r represents a radix of FFT/IFFT calculation, each of B s−1 , B s−2 , B 1 , B 0 is a radix-based digit, and N represents a number of points of FFT/IFFT calculation.

9. The method of claim 1 , further comprising

for each calculation, obtaining data from a memory with a corresponding sequence number according to the sequence number,

inputting the data into ports for short DFT sequence calculator without reordering the data,

outputting, calculation results from the calculator, to corresponding memories according to the sequence number of output ports.

10. The method of claim 1 , wherein the FFT/IFFT calculation has a length of an integer power of 2.

11. The method of claim 4 , further comprising

reordering the set of data from the corresponding memory locations by a selector, wherein a number of selectable paths of the selector are smaller than the radix of the FFT/IFFT calculation;

wherein performing the FFT/IFFT calculation further comprises performing the short DFT sequence calculation on the set of reordered data.

12. The method of claim 1 , wherein performing the FFT/IFFT calculation includes performing a FFT/IFFT butterfly calculation.

13. A circuit for performing Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT), comprising:

an address calculating unit, configured to convert a set of reversal-order or a set of natural-order addresses of FFT/IFFT data to a set of addresses in a radix-based numeral representation;

wherein the address calculating unit is further configured to calculate sequence numbers of a plurality of memory locations for buffering a set of data for a parallel calculation, by accumulating or subtracting each digit of the set of addresses in the radix-based numeral representation and then preforming a modulo operation on the accumulation or subtraction results, wherein the radix represents a length of short DFT sequence for the parallel calculation in a FFT/IFFT calculation;

an interface unit configured to store the FFT/IFFT data simultaneously and respectively into corresponding memory locations indicated by the calculated sequence numbers; and

a FFT/IFFT calculation unit, configured to perform a FFT/IFFT calculation, comprising

a short DFT sequence calculator configured to:

retrieve corresponding data from the memory, directly perform a short DFT sequence calculation for the data, modify the calculated data with a modified twiddle factor, in-place store the modified data back to the memory directly;

repeat the short DFT sequence calculation, until the whole FFT/IFFT calculation completes.

14. The circuit of claim 13 , wherein the calculated sequence numbers of the plurality of memory locations are cyclical shifts of data sequence numbers used in the short DFT sequence calculation.

15. The circuit of claim 13 , wherein each modified data for the short DFT sequence calculation are directly inputted into an input port corresponding to the FFT/IFFT calculation unit without reordering the data;

Wherein the circuit does not include a selector.

16. The circuit of claim 14 , wherein each digit of the set of addresses in the radix-based numeral representation of the data comprises a plurality of bits, wherein before calculating the sequence numbers of a plurality the memory locations, the circuit further comprises:

a converter, configured to convert each digit by performing XOR operation on two of the plurality of bits of each digit, wherein

the address calculating unit is further configure to calculate sequence numbers of a plurality of memory locations for buffering a set of data for a parallel calculation, by accumulating or subtracting all the converted digits of the set of addresses in the radix-based numeral representation of each data and then modulo the accumulation or subtraction results; wherein the calculated sequence numbers of the plurality of memory locations are a part of cyclical shifts of data sequence numbers used in one short DFT sequence calculation.

17. The circuit of claim 13 , further comprising

a first multiplier, configured to modify the data to be treated with the short DFT sequence calculation with a first modifying factor, wherein the first modifying is represented as exp[(j×(B×n)r×2pi/r), n=0, 1, 2 . . . r−1;

a twiddling unit, configured to treat the modified sequence with a twiddle factor exp[(−j×(B i ×(B i−1 B i−2 . . . B 1 B 0 )×r^(s−i))×2pi/N)];

where the short DFT sequence calculator is further configured to perform the short DFT sequence calculation on the treated sequence;

a second multiplier, configured to modify the data after DFT calculation with a second modifying factor, wherein the second modifying factor is represented as exp[(j×(B×k) r ×2pi/r)+(−j×(B×B) r ×2pi/r)], wherein B=(ΣB s ) r , (s≠i−1), i represents a stage of FFT/IFFT calculation, the data have an address of B s−1 B s−2 B i . . . B 1 B 0 , and Bi=0, 1, 2 . . . r−1, r represents the radix of FFT calculation, each of B s−1 , B s−2 , B 1 , B 0 is a radix-based digit, and N represents a number of points of FFT/IFFT calculation.

18. The circuit of claim 13 , further comprising:

a multiplexer configured to modify the data calculated by the short DFT sequence calculation with the modified twiddle factor, wherein the modified twiddle factor is represented as exp[(−j×(B i+1 ×(B i B i−1 . . . B 1 B 0 )×r^(s−i))×2pi/N)+(j×(B×k) r ×2pi/r)+(j×(C×n) r ×2pi/r)+(−j×(B×B) r ×2pi/r)], wherein B=(ΣB s ) r , (s≠i−1), C=(ΣB s ) r , (s≠i), i represents a stage of FFT/IFFT calculation, the data have an address of B s−1 B s−2 B i . . . B 1 B 0 , and Bi=0, 1, 2 . . . r−1, r represents the radix of FFT/IFFT calculation, each of B s−1 , B s−2 , B 1 , B 0 is a radix-based digit, and N represents the number of points of FFT/IFFT calculation.

19. The circuit of claim 13 , wherein a list between values of twiddle factors and index is stored in the memory, and the circuit further comprises

a modifying unit configured to obtain an updated index by adding a higher R bits of the twiddle factor with a modified value, wherein the updated index corresponds to the modified twiddle factor, and

modify the data after DFT calculation with the modified twiddle factor, wherein R is represented as log 2(r), and r represents a radix of a FFT calculation.

20. The circuit of claim 13 , wherein the set of data comprises data to be computed for a first stage of FFT/IFFT calculation, and the circuit comprises

a weighing unit configured to weigh the data with an equation of exp(j×(C×n) r ×2pi/r), wherein n=B 0 , C=(ΣB s ), (s≠0) during inputting, wherein the data have an address of B s−1 B s−2 B i . . . B 1 B 0 , and Bi=0, 1, 2 . . . r−1, r represents a radix of FFT/IFFT calculation, each of B s−1 , B s−2 , B 1 , B 0 is a radix-based digit, and N represents the number of points of FFT/IFFT calculation.

21. The circuit of claim 13 , wherein the interface unit is further configured to

for each calculation, obtain a data from a memory with a corresponding sequence number according to the sequence number,

inputting the data into ports for short DFT sequence calculator from ports of the short DFT sequence calculator without reordering the data, and

output, calculation results from the calculator, to corresponding memories according to the sequence number of output ports.

22. The circuit of claim 13 , wherein the FFT/IFFT calculation has a length of an integer power of 2.

23. The circuit of claim 16 , further comprising

a selector configured to reorder the set of data from the corresponding memory locations, wherein a number of selectable paths of the selector are smaller than the radix of the FFT/IFFT calculation;

wherein the FFT/IFFT calculation unit is further configured to perform the FFT/IFFT calculation on the set of reordered data.

24. The circuit of claim 13 , wherein performing the FFT/IFFT calculation includes performing a FFT/IFFT butterfly calculation.

25. A receiver including circuit for performing Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT) according to claim 13 .

26. A Signal generator including circuit for performing Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT) according to claim 13 .

27. A non-transitory computer-readable medium comprising instructions executable by at least one processor to perform a method comprising:

controlling an address calculating unit of the at least one processor to convert a set of reversal-order or set of natural-order addresses of FFT/IFFT data to set of addresses in a radix-based numeral representation;

controlling the address calculating unit to calculate sequence numbers of a plurality of memory locations for buffering a set of data for a parallel calculation, by accumulating or subtracting all digits of the set of addresses in the radix-based numeral representation and then performing a modulo on the accumulation or subtraction results, wherein the radix represents a base for a length of short DFT sequence for the parallel calculation in a FFT/IFFT calculation;

controlling an interface unit of the at least one processor to store the FFT/IFFT data simultaneously and respectively into the corresponding memory locations indicated by the calculated sequence numbers; and

controlling an FFT/IFFT calculation unit of the at least one processor to perform FFT/IFFT calculation, comprising

performing a short DFT sequence calculation, comprising:

retrieving corresponding data from the memory, inputting directly the corresponding data into a short DFT sequence calculator for calculation, modifying the calculated data with a modified twiddle factor, in-place storing the modified data back to the memory directly;

repeating the short DFT sequence calculation, until the whole FFT/IFFT calculation completes.