IP Library Granted Patent US 9,769,939
Granted Patent B2
US 9,769,939 · App. 15/195,533 · Granted Sep 19, 2017

Managed connectivity in electrical systems and methods thereof

Inventors: Joseph C. Coffey (Burnsville, MN); Loren J. Mattson (Richfield, MN)
Assignee: CommScope Technologies LLC
H05K5/0026H01R12/70H01R13/518H01R13/641H01R13/6658H01R24/60H01R24/64H01R25/006H04Q1/13H05K5/0017H01R2107/00H01R2201/04Y10S439/955Y10T29/49147
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Quick Facts
Patent No.
US 9,769,939
App. No.
15/195,533
Filed
Jun 28, 2016
Granted
Sep 19, 2017
Kind
B2
Art Unit
2831
USPC
439/761
Abstract

An electrical connector arrangement includes a storage device coupled to a connector housing. The storage device is configured to store physical layer information pertaining to the electrical connector arrangement. The storage device also has contacts that enable the physical layer information to be read from the storage device by a media reading interface. A connector assembly includes at least one receptacle assembly; a printed circuit board; and a media reading interface.

Claims (29)

1. A patch panel comprising:

a frame having a front face and a rear face opposite the front face, the frame defining apertures extending between the front and rear faces;

a fascia coupled to the front face of the frame, the fascia defining port openings that align with the apertures defined by the frame;

a circuit board coupled to the frame, the circuit board having first and second major surfaces extending parallel with the front and rear faces of the frame;

a plurality of media reading interfaces operably coupled to the circuit board, each media reading interface being aligned with one of the apertures of the frame;

a plurality of jacks coupled to the frame and extending rearwardly of the frame, each of the jacks including plug contacts that are electrically isolated from the media reading interfaces; and

a network connector disposed at the second major surface of the circuit board.

2. The patch panel of claim 1 , further comprising a processor module mounted to the second major surface of the circuit board at the network connector, the processor module including a housing holding a processor, the processor module defining a network port at an opposite side of the processor module from the network connector.

3. The patch panel of claim 1 , wherein the media reading interfaces are offset from the port openings and the frame apertures, wherein portions of the media reading interfaces are deflected away from the port openings and the frame apertures by insertion of a plug through the port openings and the frame apertures.

4. The patch panel of claim 1 , wherein the media reading interfaces are disposed at the second major surface of the circuit board.

5. The patch panel of claim 1 , wherein the media reading interfaces are disposed at the first major surface of the circuit board.

6. The patch panel of claim 1 , further comprising a plate member including forwardly extending arms that mount to a rear of the frame, the plate member having major surfaces extending perpendicular to the major surfaces of the circuit board, the major surfaces defining pairs of apertures therein.

7. A patch panel comprising:

a forward portion having a forward-facing port face that defines a row of ports, the forward portion including a fascia;

a rearward portion configured to mount at a rear of the forward portion, the rearward portion carrying a plurality of jacks, each jack having a plurality of plug contacts accessible through sockets, the rearward portion positioning the jacks in alignment with the ports of the forward portion when the rearward portion mounts to the forward portion so that each socket is accessible through one of the ports, the rearward portion defining a cutout section; and

a circuit board disposed between the forward and rearward portions, the circuit board having first and second major surfaces that are parallel to the forward-facing port face of the forward portion, the circuit board carrying a plurality of media reading interfaces, each media reading interface being aligned with one of the jacks, the media reading interfaces being isolated from the plug contacts of the jacks, the circuit board including a network connector extending rearwardly from the second major surface through the cutout section defined by the rearward portion.

8. The patch panel of claim 1 , wherein each media reading interface includes an electrically conductive contact member.

9. The patch panel of claim 8 , wherein each media reading interface includes a plurality of electrically conductive contact members.

10. The patch panel of claim 9 , wherein each media reading interface includes three electrically conductive contact members.

11. The patch panel of claim 9 , wherein each media reading interface includes four electrically conductive contact members.

12. The patch panel of claim 7 , further comprising a processor module electrically connected to the network connector of the circuit board, the processor module including a housing holding a processor, the processor module defining a network port at an opposite side of the processor module from the network connector.

13. The patch panel of claim 12 , wherein the rearward portion includes a frame that defines a row of apertures that align with the row of ports of the forward portion.

14. The patch panel of claim 12 , wherein the media reading interfaces are disposed at the second major surface of the circuit board.

15. The patch panel of claim 12 , wherein the media reading interfaces are disposed at the first major surface of the circuit board.

16. The patch panel of claim 12 , wherein the fascia is removable from the frame.

17. The patch panel of claim 12 , wherein each media reading interface includes an electrically conductive contact member.

18. The patch panel of claim 17 , wherein each media reading interface includes a plurality of electrically conductive contact members.

19. The patch panel of claim 18 , wherein each media reading interface includes three electrically conductive contact members.

20. The patch panel of claim 18 , wherein each media reading interface includes four electrically conductive contact members.

Assignments (6)
RELEASE OF SECURITY INTEREST AT REEL/FRAME 049905/0504 Recorded Dec 19, 2024
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: ARRIS ENTERPRISES LLC (F/K/A ARRIS ENTERPRISES, INC.); ARRIS TECHNOLOGY, INC.; ARRIS SOLUTIONS, INC.; COMMSCOPE, INC. OF NORTH CAROLINA; COMMSCOPE TECHNOLOGIES LLC; RUCKUS WIRELESS, LLC (F/K/A RUCKUS WIRELESS, INC.)
Reel/Frame 071477/0255 →
SECURITY INTEREST Recorded Dec 17, 2024
From: ARRIS ENTERPRISES LLC; COMMSCOPE TECHNOLOGIES LLC; COMMSCOPE INC., OF NORTH CAROLINA; OUTDOOR WIRELESS NETWORKS LLC; RUCKUS IP HOLDINGS LLC
To: APOLLO ADMINISTRATIVE AGENCY LLC
Reel/Frame 069889/0114 →
SECURITY INTEREST Recorded Nov 19, 2021
From: ARRIS SOLUTIONS, INC.; ARRIS ENTERPRISES LLC; COMMSCOPE TECHNOLOGIES LLC; COMMSCOPE, INC. OF NORTH CAROLINA; RUCKUS WIRELESS, INC.
To: WILMINGTON TRUST
Reel/Frame 060752/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 3, 2019
From: COMMSCOPE TECHNOLOGIES LLC
To: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 049892/0051 →
ABL SECURITY AGREEMENT Recorded Jul 3, 2019
From: COMMSCOPE, INC. OF NORTH CAROLINA; COMMSCOPE TECHNOLOGIES LLC; ARRIS ENTERPRISES LLC; ARRIS TECHNOLOGY, INC.; RUCKUS WIRELESS, INC.; ARRIS SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 049892/0396 →
TERM LOAN SECURITY AGREEMENT Recorded Jul 3, 2019
From: COMMSCOPE, INC. OF NORTH CAROLINA; COMMSCOPE TECHNOLOGIES LLC; ARRIS ENTERPRISES LLC; ARRIS TECHNOLOGY, INC.; RUCKUS WIRELESS, INC.; ARRIS SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 049905/0504 →
Continuity (4)
Continuation 14656801 · Mar 13, 2015
Continuation 12905689 · Oct 15, 2010
Provisional Application 61252395 · Oct 16, 2009
Related Publication 20160381816A1 · Dec 29, 2016