Logical operation circuit and memory device

1. A logical operation circuit comprising:

a magnetic tunnel junction (MTJ) element comprising a first magnetic layer, a second magnetic layer, and an intermediate layer between the first and second magnetic layers, wherein the MTJ element transitions to a first state from a second state by a first voltage being applied to the MTJ element, and the MTJ element transitions to the second state from the first state by the first voltage being applied to the MTJ element; and

a driver which is coupled to the first magnetic layer without a magnetic layer interposed and coupled to the second magnetic layer, and outputs the first voltage.

2. The circuit of claim 1 , wherein an orientation of magnetization of the first magnetic layer and an orientation of magnetization of the second magnetic layer are antiparallel in the first state.

3. The circuit of claim 1 , wherein:

an orientation of magnetization of the first magnetic layer flips by a third current which flows through the MTJ element in the second state from the second magnetic layer to the first magnetic layer,

the driver passes a selected one of a fourth current and a fifth current through the MTJ element in the second state from the second magnetic layer to the first magnetic layer,

the fourth current is larger than 1.5 times the third current, and

the third current is larger than 1.5 times the fifth current.

4. The circuit of claim 3 , wherein:

the driver applies to the MTJ element the first voltage with the second magnetic layer at a higher potential to pass a second current or the fourth current and applies to the MTJ element a second voltage with the second magnetic layer at a higher potential to pass the fifth current,

the second voltage is lower than the first voltage,

a sixth current flows through the MTJ element by application of the second voltage to the MTJ element in the first state,

the sixth current is larger than 1.5 times a first current which flows through the MTJ element in the first state from the second magnetic layer to the first magnetic layer, and

an orientation of magnetization of the second magnetic layer flips by the first current.

5. The circuit of claim 4 , wherein:

the orientation of the magnetization of the first magnetic layer and the orientation of the magnetization of the second magnetic layer are antiparallel in the first state, and

the orientation of the magnetization of the first magnetic layer and the orientation of the magnetization of the second magnetic layer are parallel in the second state.

6. The circuit of claim 4 , further comprising:

a controller which:

receives a digital signal,

applies the first voltage to the MTJ element based on a logic of the digital signal and determines in which of the first and second states the MTJ element is in after the application of the first voltage, and

applies the second voltage to the MTJ element based on the logic of the digital signal, and determines in which of the first and second states the MTJ element is in after the application of the second voltage.

7. The circuit of claim 1 , wherein:

the driver passes a selected one of a second current and a third current through the MTJ element in the first state from the second magnetic layer to the first magnetic layer,

the third current is smaller than 1.5 times a first current which flows through the MTJ element in the first state from the second magnetic layer to the first magnetic layer, and

an orientation of magnetization of the second magnetic layer flips by the first current.

8. The circuit of claim 7 , wherein:

an orientation of the magnetization of the first magnetic layer flips by a fourth current which flows through the MTJ element in the second state from the second magnetic layer to the first magnetic layer,

the driver:

applies the first voltage with the second magnetic layer at a higher potential to the MTJ element to pass the second current or a fifth current, and

applies a second voltage with the second magnetic layer at a higher potential to the MTJ element to pass the third current or a sixth current,

the second voltage is lower than the first voltage,

the fifth current is larger than 1.5 times the fourth current, and

the sixth current is larger than 1.5 times the fourth current.

9. The circuit of claim 8 , wherein:

the orientation of the magnetization of the first magnetic layer and the orientation of the magnetization of the second magnetic layer are antiparallel in the first state, and

the orientation of the magnetization of the first magnetic layer and the orientation of the magnetization of the second magnetic layer are parallel in the second state.

10. The circuit of claim 9 , further comprising:

a controller which:

receives a digital signal,

applies the first voltage to the MTJ element based on a logic of the digital signal and determines in which of the first and second states the MTJ element is in after the application of the first voltage, and

applies the second voltage to the MTJ element based on the logic of the digital signal, and determines in which of the first and second states the MTJ element is in after the application of the second voltage.

11. The device of claim 1 , wherein:

an orientation of magnetization of the second magnetic layer flips by a first current which flows through the MTJ element in the first state from the second magnetic layer to the first magnetic layer,

the driver passes a second current through the MTJ element in the first state from the second magnetic layer to the first magnetic layer, and

a magnitude of the second current is larger than 1.5 times a magnitude of the first current.

12. A memory device comprising:

a first to sixth interconnects;

a first MTJ element coupled between the first and second interconnects through a transistor;

a second MTJ element coupled between the third and fourth interconnects through a transistor;

a third MTJ element coupled between the fifth and sixth interconnects through a transistor;

a current source coupled to the first, third, and fifth interconnects through respective transistors;

a current sink coupled to the first, third, and fifth interconnects through respective transistors;

a first transistor and a second transistor coupled in series between the second and fourth interconnects; and

a third transistor between a connection node of the first and second transistors and the sixth interconnect,

wherein:

the current source is configured to output a first voltage and a second voltage different from the first voltage,

a state of the third MTJ element flips when a current higher than a first value flows through the third MTJ element,

the first and second MTJ elements have a first state and a second state different from the first state,

the state of the third MTJ element flips when the first voltage is output while the first and second MTJ elements are in the first state,

the state of the third MTJ element flips when the second voltage is output while the first MTJ element is in the first state and the second MTJ element is in the second state,

when the first voltage is output while the first MTJ element is in the first state and the second MTJ element is in the second state, the third MTJ element maintains the state prior to the output of the first voltage until an end of the output of the first voltage, and

when the first voltage is output while the first and second MTJ elements are in the second state, the third MTJ element maintains the state prior to the output of the first voltage until the end of the output of the first voltage.

13. The device of claim 12 , further comprising:

a second current sink coupled to the second, fourth, and sixth interconnects through respective transistors.

14. The device of claim 12 , wherein the first and second transistors are on while the current source and the current sink are operating.

15. The device of claim 14 , wherein the current sink is electrically coupled to the fifth interconnect while the current source is electrically coupled to the first and third interconnects.