Co-fabrication of vertical diodes and fin field effect transistors on the same substrate

1. A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:

forming a channel layer stack on a heavily doped layer;

forming one or more fin trenches in the channel layer stack;

oxidizing at least a portion of the channel layer stack inside the one or more fin trenches to form a dummy layer liner;

forming a vertical fin in at least one of the one or more fin trenches with the dummy layer liner;

forming one or more diode trenches in the channel layer stack;

oxidizing at least a portion of the channel layer stack inside the one or more diode trenches to form a dummy layer liner;

forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches with the dummy layer liner; and

forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

2. The method of claim 1 , further comprising:

thinning an upper portion of at least one of the vertical fins formed in the at least one of the one or more fin trenches; and

forming a top source drain on the thinned portion of the at least one of the vertical fins.

3. The method of claim 1 , wherein the channel layer stack includes a dummy gate layer and a bottom spacer layer, and the method further comprises:

removing the dummy gate layer and the dummy layer liner from at least one of the vertical fins formed in the at least one of the one or more fin trenches with the dummy layer liner to expose the sidewalls of the at least one vertical fin;

forming a high-K dielectric layer on at least an exposed surface of the bottom spacer layer and the sidewalls of the at least one vertical fin;

forming a work function layer on the high-K dielectric layer; and

forming a gate metal layer on the work function layer.

4. The method of claim 3 , further comprising removing at least a portion of the gate metal layer, work function layer, and high-K dielectric layer on the exposed surface of the bottom spacer layer.

5. The method of claim 3 , further comprising forming a metal fill on the bottom spacer layer, where the metal fill is in contact with the gate metal layer.

6. The method of claim 1 , wherein the one or more vertical fins are formed by epitaxial growth from the heavily doped layer, and the first semiconductor segment is formed by epitaxial growth from the heavily doped layer.

7. The method of claim 6 , wherein the top surface of the one or more vertical fins have a <100> crystal orientation.

8. The method of claim 1 , wherein the second semiconductor segment is epitaxially grown on the first semiconductor segment, and has a top surface with a <100> crystal orientation.

9. A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:

forming a counter-doped layer on a substrate and a heavily doped layer on the counter-doped layer;

forming a bottom spacer layer on the heavily doped layer;

forming a dummy gate layer on the bottom spacer layer;

forming a top spacer layer on the dummy gate layer;

forming one or more fin trenches, where at least one of the one or more fin trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;

oxidizing at least a portion of the exposed portion of the dummy gate layer inside the one or more fin trenches to form a dummy layer liner;

forming a vertical fin in at least one of the one or more fin trenches with the dummy layer liner;

forming one or more diode trenches, where at least one of the one or more diode trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;

oxidizing at least a portion of the exposed portion of the dummy gate layer inside the one or more diode trenches to form a dummy layer liner;

forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches with the dummy layer liner; and

forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

10. The method of claim 9 , further comprising forming a top source/drain on a top of the one or more vertical fins.

11. The method of claim 9 , further comprising forming one or more shallow trench isolation regions through the heavily doped layer and counter-doped layer to form a plurality of electrically separated heavily doped regions.

12. The method of claim 9 , wherein the dummy layer liner provides protect to the one or more vertical fins during epitaxial growth.

13. The method of claim 9 , further comprising:

removing the dummy gate layer and the dummy layer liner from at least one of the vertical fins formed in the at least one of the one or more fin trenches with the dummy layer liner to expose the sidewalls of the at least one vertical fin;

forming a conformal high-K dielectric layer on at least an exposed surface of the sidewalls of the at least one vertical fin;

forming a conformal work function layer on the high-K dielectric layer; and

forming a conformal gate metal layer on the work function layer.

14. The method of claim 13 , where the conformal high-K dielectric layer, conformal work function layer, and/or conformal gate metal layer is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof.