Actively preventing charge induced leakage of semiconductor devices
A structure for preventing charge induced leakage of a semiconductor device includes a shield separated from a first interconnect by at least a first lateral spacing and separated from a second interconnect by at least a second lateral spacing. The first interconnect is connected to a first junction and the second interconnect is connected to a second junction. A shield bias is connected to the shield to terminate an electromagnetic field on the shield. The shield between the first and second lateral spacings has a minimum width to substantially prevent formation of a conductive channel between the first and second junctions. The shield may be formed over a portion of the first junction and over a portion of the second junction to substantially prevent formation of another conductive channel between the first and second junctions at a location that does not have the first and second lateral spacings.
1. A structure for preventing charge induced leakage of a semiconductor device comprising:
a shield on the semiconductor device, wherein the shield is separated from a first metal interconnect by at least a first lateral spacing and separated from a second metal interconnect by at least a second lateral spacing, the first metal interconnect connects a first doped junction to another first doped junction, and the second metal interconnect connects a second doped junction to another second doped junction, the shield surrounds each of a plurality of first contacts to the first metal interconnect and a plurality of second contacts to the second metal interconnect, the shield configured to contact at least one of the first metal interconnect and the second metal interconnect at all locations where the shield has a vertical overlap between with the respective first metal interconnect and second metal interconnect, the vertical overlap orthogonal to the first lateral spacing and the second lateral spacing; and
a shield bias connected to the shield to terminate an electromagnetic (EM) field on a surface of the shield wherein the shield between the first lateral spacing and the second lateral spacing has a minimum width to prevent formation of a conductive channel between the first doped junction and the second doped junction.
2. The structure of claim 1 wherein the first doped junction is biased at a different potential than the second doped junction.
3. The structure of claim 1 wherein the shield bias has a different potential than a potential of an accumulated charge on the semiconductor device.
4. The structure of claim 1 wherein the shield bias is equal to a substrate bias.
5. The structure of claim 1 wherein the first doped junction and the second doped junction are PFET junctions.
6. The structure of claim 1 wherein the shield partially surrounds a bond pad to prevent the formation of the conductive channel.
7. The structure of claim 1 wherein the shield is formed over a portion of the first doped junction and over a portion of the second doped junction to substantially prevent formation of another conductive channel between the first doped junction and the second doped junction at a location that does not have the first and second lateral spacings.
8. The structure of claim 1 wherein the shield is a same conductive layer as at least one of the first metal interconnect and the second metal interconnect, and the shield is electrically isolated from the first and second metal interconnects.
9. The structure of claim 8 wherein the structure includes a through-silicon-via.
10. The structure of claim 1 wherein the semiconductor device is a microelectromechanical system (MEMS).
11. The structure of claim 10 wherein the MEMS is a piezo-resistive transducer.
12. The structure of claim 1 wherein the shield includes Titanium Nitride.