Magnetic field sensor with delayed output
Apparatuses, systems, and methods that provide a delayed output signal with reduced sampling error are described. Embodiments include a clock circuit that generates a sample clock signal having a predetermined sample clock period. A sampling circuit may generate samples of a received signal during each sample clock period. An interpolation circuit may estimate a value of the received signal at times between the samples of the received signal based on at least a first sample and a second sample of the received signal. The interpolation circuit may estimate a time that the received signal crosses a threshold, and determine a time delta between the first sample and the estimated time that the received signal crosses the threshold. A delay circuit to generate a time delay substantially equal to the time delta is also included. An output signal changes state after the generated time delay.
1. A system comprising:
a clock circuit generating a sample clock signal having a predetermined sample clock period;
a sampling circuit to generate samples of a received signal during each sample clock period;
an interpolation circuit to:
estimate at least one value of the received signal at times between the samples of the received signal, the at least one estimated value corresponding to a threshold value and based on at least a first sample and a second sample of the received signal;
estimate a time that the received signal crosses the threshold by using the estimated values; and
determine a time delta between the first sample and the estimated time that the received signal crosses the threshold; and
a delay circuit to generate a time delay substantially equal to the time delta; and
a synchronization circuit to periodically synchronize the delay circuit so that a maximum delay generated by the delay circuit is substantially equal to the sample clock period, wherein the synchronization circuit comprises a control feedback loop.
2. The system of claim 1 wherein the delay circuit is further configured to generate the time delay during a clock period following the second sample.
3. The system of claim 1 further comprising a circuit to generate a state transition of an output signal after the time delay.
4. The system of claim 1 wherein an output of the delay circuit has a resolution that is a fraction of the clock period.
5. The system of claim 4 wherein the delay circuit has a resolution that is ½ x times the sample clock period, where x is a non-zero integer.
6. The system of claim 1 wherein delay circuit includes one or more inputs to receive one or more control signals representing the time delay.
7. The system of claim 6 wherein the one or more inputs are digital inputs.
8. The system of claim 6 further comprising a state machine to generate the one or more control signals.
9. The system of claim 1 wherein the discrete time control feedback loop comprises a phase comparator and a variable current source.
10. A magnetic field sensor comprising:
a clock circuit generating a sample clock signal having a predetermined sample clock period;
a sampling circuit to generate, during each sample clock period, samples of a magnetic field signal representing an external magnetic field;
an interpolation circuit to:
estimate at least one value of the received signal at times between the samples of the received signal, the at least one estimated value corresponding to a threshold value and based on at least a first sample and a second sample of the received signal;
estimate a time that the received signal crosses the threshold by using the estimated values; and
determine a time delta between the first sample and the estimated time that the received signal crosses the threshold; and
a delay circuit to generate a time delay substantially equal to the time delta; and
a synchronization circuit to periodically synchronize the delay circuit so that a maximum delay generated by the delay circuit is substantially equal to the sample clock period, wherein the synchronization circuit comprises a control feedback loop.
11. The magnetic field sensor of claim 10 wherein the delay circuit is further configured to generate the time delay following a second sample clock period after the first sample clock period.
12. The magnetic field sensor of claim 11 further comprising a circuit to generate a state transition of an output signal after the time delay.
13. The magnetic field sensor of claim 10 wherein the delay circuit has a resolution that is a fraction of the sample clock period.
14. A method comprising:
generating a sample clock signal having a predetermined sample clock period;
generating samples of a received signal during each sample clock period to produce a sampled signal;
estimating at least one value of the received signal at times between the samples of the received signal, the at least one estimated value corresponding to a threshold value and based on at least a first sample and a second sample of the received signal;
estimating a time that the received signal crosses the threshold;
determining a time delta between the first sample and the estimated time that the received signal crosses the threshold;
generating a delayed output signal having a state transition occurring at a time substantially equal to the time delta following the second sample; and
periodically synchronizing, by a synchronization circuit, the delayed output signal so that a maximum delay of the delayed output signal is substantially equal to the sample clock period wherein the synchronization circuit comprises a control feedback loop.
15. The method of claim 14 further comprising generating the state transition of the delayed output signal during a clock period following the second sample.
16. The method of claim 14 wherein estimating the at least one value includes interpolating a point of the received signal between the first and second samples based on an interpolation function.
17. An apparatus comprising:
a clock circuit generating a sample clock signal having a predetermined sample clock period;
a sampling circuit to generate samples of a received signal during each sample clock period;
an interpolation circuit to:
estimate at least one value of the received signal at times between the samples of the received signal, the at least one estimated value corresponding to a threshold value and based on at least a first sample and a second sample of the received signal;
estimate a time that the received signal crosses the threshold by using the estimated values; and
determine a time delta between the first sample and the estimated time that the received signal crosses the threshold; and
means for generating a delayed output signal having a state transition during a second sample clock period following the first sample clock period, the delayed output signal being delayed by a time substantially equal to the time delta during a clock period following the second sample; and
a synchronization circuit to periodically synchronize the delay circuit so that a maximum delay generated by the delay circuit is substantially equal to the sample clock period, wherein the synchronization circuit comprises a control feedback loop.
18. The apparatus of claim 17 wherein the second clock period follows immediately after the first clock period.