Controller of nonvolatile semiconductor memory

1. A controller comprising:

a decoder that converts a plurality of error correction code (ECC) frames read out from a nonvolatile semiconductor memory into likelihood information based on a set table among a plurality of log-likelihood ratio (LLR) tables, generates a plurality of decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful;

a calculation section that generates calculation data based on an ECC frame of calculation target among the plurality of decoded ECC frames and an ECC frame before decoded, which corresponds to the ECC frame of the calculation target, the ECC frame of calculation target being a successfully-decoded ECC frame;

a table creation section that creates a new LLR table by executing statistical calculation based on the calculation data generated by the calculation section and sets the new LLR table to the decoder; and

a control section that controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful,

wherein the decoder decodes the ECC frames based on the new LLR table,

wherein the ECC frame before decoded includes a readout level of each of a plurality of bits,

wherein the calculation section generates a channel matrix by counting a number of times of a combination of a correct bit value and a readout level for each bit included in the ECC frame of the calculation target based on the ECC frame of the calculation target and the ECC frame before decoded, and

wherein the table creation section statistically calculates, based on the channel matrix, a likelihood of the correct bit value for each of the readout level included in the ECC frame of the calculation target, and creates the new LLR table.

2. The controller of claim 1 ,

wherein the control section sets each of the plurality of decoded ECC frames to the calculation target in the calculation section only once when the decoding is successful.

3. The controller of claim 1 ,

wherein the control section sets an ECC frame in which the decoding is successful and the calculation has not been applied yet to the calculation target in the calculation section, and excludes an ECC frame in which the decoding is unsuccessful and an ECC frame in which the decoding is successful but the calculation has been already applied from the calculation target in the calculation section.

4. The controller of claim 1 ,

wherein the control section executes an initialization for a control of the calculation target when a plurality of new ECC frames are read out from the nonvolatile semiconductor memory.

5. The controller of claim 1 ,

wherein the table creation section is realized by firmware executed by a processor,

wherein the firmware controls the control section, generates the new LLR table based on a result of the decoding by the decoder and the calculation data generated by the calculation section, sets the new LLR table to the decoder and causes the decoder to retry the decoding, and

wherein the control section is configured by hardware.

6. The controller of claim 1 ,

wherein the table creation section is configured by hardware, controls the control section, creates the new LLR table based on a result of the decoding by the decoder and the calculation data generated by the calculation section, sets the new LLR table to the decoder and causes the decoder to retry the decoding, and

wherein the control section is configured by hardware.

7. The controller of claim 1 , wherein the decoder is a low density parity check (LDPC) decoder, and wherein the controller further comprises a Bose-Chaudhuri-Hocquenghem (BCH) decoder that performs BCH decoding for the plurality of decoded ECC frames when the decoding for all the plurality of ECC frames is successful.

8. The controller of claim 1 ,

wherein the calculation section comprises a plurality of switches corresponding to each of the plurality of decoded ECC frames, and

wherein the control section controls whether or not each of the plurality of decoded ECC frames becomes the calculation target by switching on/off the plurality of switches.

9. A semiconductor memory device comprising:

a nonvolatile semiconductor memory; and

a controller that controls the nonvolatile semiconductor memory,

wherein the controller comprises:

a decoder that converts a plurality of error correction code (ECC) frames read out from a nonvolatile semiconductor memory into likelihood information based on a set table among a plurality of tables, generates a plurality of decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful;

a calculation section that generates calculation data based on an ECC frame of calculation target among the plurality of decoded ECC frames and an ECC frame before decoded, which corresponds to the ECC frame of the calculation target, the ECC frame of calculation target being a successfully-decoded ECC frame;

a table creation section that creates a new log-likelihood ratio (LLR) table by executing statistical calculation based on the calculation data generated by the calculation section and sets the new LLR table to the decoder; and

a control section that controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful,

the decoder decodes the ECC frames based on the new LLR table,

the ECC frame before decoded includes a readout level of each of a plurality of bits,

the calculation section generates a channel matrix by counting a number of times of a combination of a correct bit value and a readout level for each bit included in the ECC frame of the calculation target based on the ECC frame of the calculation target and the ECC frame before decoded, and

the table creation section statistically calculates, based on the channel matrix, a likelihood of the correct bit value for each of the readout level included in the ECC frame of the calculation target, and creates the new LLR table.

10. The semiconductor memory device of claim 9 ,

wherein the control section sets each of the plurality of decoded ECC frames to the calculation target in the calculation section only once when the decoding is successful.

11. The semiconductor memory device of claim 9 ,

wherein the control section sets an ECC frame in which the decoding is successful and the calculation has not been applied yet to the calculation target in the calculation section, and excludes an ECC frame in which the decoding is unsuccessful and an ECC frame in which the decoding is successful but the calculation has been already applied from the calculation target in the calculation section.

12. The semiconductor memory device of claim 9 ,

wherein the control section executes an initialization for a control of the calculation target when a plurality of new ECC frames are read out from the nonvolatile semiconductor memory.

13. The semiconductor memory device of claim 9 ,

wherein the table creation section is realize by firmware executed by a processor,

wherein the firmware controls the control section, generates the new LLR table based on a result of the decoding by the decoder and the calculation data generated by the calculation section, sets the new LLR table to the decoder and causes the decoder to retry the decoding, and

wherein the control section is configured by hardware.

14. The semiconductor memory device of claim 9 ,

wherein the table creation section is configured by hardware, controls the control section, creates the new LLR table based on a result of the decoding by the decoder and the calculation data generated by the calculation section, sets the new LLR table to the decoder and causes the decoder to retry the decoding, and

wherein the control section is configured by hardware.

15. The semiconductor memory device of claim 9 , wherein the decoder is a low density parity check (LDPC) decoder, and wherein the controller further comprises a Bose-Chaudhuri-Hocquenghem (BCH) decoder that performs BCH decoding for the plurality of decoded ECC frames when the decoding for all the plurality of ECC frames is successful.

16. The semiconductor memory device of claim 9 ,

wherein the calculation section comprises a plurality of switches corresponding to each of the plurality of decoded ECC frames, and

wherein the control section controls whether or not each of the plurality of decoded ECC frames becomes the calculation target by switching on/off the plurality of switches.