System architecture for machine vision on moving platforms

1. An integrated computing system for processing machine vision data and performing active control of a mobile platform, the computer system comprising:

a first plurality of sensors configured to acquire inertial and positional data related to the mobile platform;

a first plurality of co-processors communicatively coupled to the first plurality of sensors, the first plurality of co-processors including a hardware logic configured to control the acquisition of the inertial and positional data and configured to analyze the acquired inertial and positional data;

a second plurality of sensors configured to acquire image data related to the mobile platform;

a second plurality of co-processors communicatively coupled to the second plurality of sensors, the second plurality of co-processors including a hardware logic configured to control the acquisition of the image data and configured to analyze the acquired image data;

a plurality of arrays of memory blocks for storing the acquired image data;

state vector module to perform state management operation for the acquired inertial and positional data in a local memory, wherein the state management operation is performed using a state vector and wherein the state vector module coordinates sharing and updating the acquired inertial and positional data in a parallel fashion between the first and second plurality of co-processors; and

a plurality of memory controllers configured to control access to the plurality of arrays of memory blocks, wherein the plurality of memory controllers are communicatively coupled to the second plurality of co-processors and communicatively coupled to the state vector module and wherein the plurality of memory controllers are further configured to control a plurality of image processing pipeline components configured to process metatagged data through a multi-functional pipeline.

2. The integrated computing system of claim 1 , wherein at least the first plurality of co-processors, second plurality of co-processors, state vector module and the plurality of memory controllers comprise a system-on-module.

3. The integrated computing system of claim 1 , wherein at least the first plurality of co-processors, second plurality of co-processors, state vector module and the plurality of memory controllers comprise a Field Programmable Gate Array (FPGA).

4. The integrated computing system of claim 1 , wherein each of the second plurality of co-processors is communicatively coupled to each of the second plurality of sensors.

5. The integrated computing system of claim 1 , wherein the hardware logic of the first plurality of processors is further configured to perform a plurality of movement control functions related to the mobile platform.

6. The integrated computing system of claim 1 , wherein the state management operation is performed by the state vector module in a non-blocking manner.

7. The integrated computing system of claim 2 , further comprising an embedded Ethernet packet routing controller.

8. The integrated computing system of claim 1 , wherein the first plurality of co-processors is configured to establish one of the following operating modes: reset mode, sleep mode, runtime mode, chirp acquisition mode and init mode.

9. The integrated computing system of claim 7 , wherein each of the plurality of arrays of memory blocks comprises at least one of flash memory, dynamic random access memory (“DRAM”), or double data rate DRAM.

10. An integrated computing system for processing machine vision data and performing active control of a mobile platform, the computer system comprising:

a first plurality of sensors configured to acquire inertial and positional data related to the mobile platform;

a second plurality of sensors configured to acquire image data related to the mobile platform;

a system on chip comprising:

a first plurality of co-processors communicatively coupled to the first plurality of sensors, the first plurality of co-processors including a hardware logic configured to control the acquisition of the inertial and positional data and configured to analyze the acquired inertial and positional data;

a second plurality of co-processors communicatively coupled to the second plurality of sensors, the second plurality of co-processors including a hardware logic configured to control the acquisition of the image data and configured to analyze the acquired image data;

state vector module to perform state management operation for the acquired inertial and positional data in a local on chip memory, wherein the state management operation is performed using a state vector and wherein the state vector module coordinates sharing and updating the acquired inertial and positional data in a parallel fashion between the first and second plurality of co-processors; and

a plurality of arrays of memory blocks for storing the acquired image data, wherein the plurality of arrays of memory blocks is external to the system on chip; and

a plurality of memory controllers configured to control access to the plurality of arrays of memory blocks, wherein the plurality of memory controllers are communicatively coupled to the second plurality of co-processors and communicatively coupled to the state vector module and wherein the plurality of memory controllers are further configured to control a plurality of image processing pipeline components configured to process metatagged data through a multi-functional pipeline.

11. The integrated computing system of claim 10 , wherein each of the plurality of arrays of memory blocks comprises at least one of flash memory, dynamic random access memory (“DRAM”), or double data rate DRAM.

12. The integrated computing system of claim 10 , wherein the hardware logic of the second plurality of co-processors is further configured to perform a metatagging function, wherein the metatagging function comprises (1) packaging the machine vision data received from the second plurality of sensors into a plurality of image data streams and (2) inserting into each image a metatag describing the corresponding image and wherein the metatagging function is performed in accordance with data localization needed to perform parallel processing of the plurality of data streams.

13. The integrated computing system of claim 10 , wherein the local on chip memory comprises a multi port RAM.

14. The integrated computing system of claim 10 ,

wherein the system on chip further comprises a data sequencing interface communicatively coupled to the second plurality of co-processors and the state vector module.