IP Library Granted Patent US 9,831,210
Granted Patent B2
US 9,831,210 · App. 15/362,246 · Granted Nov 28, 2017

Electronic device and electronic apparatus

Inventors: Taiki Uemura (Kawasaki, JP); Seiki Sakuyama (Yamato, JP)
Assignee: FUJITSU LIMITED
H01L24/17B23K35/262B23K35/302C22C9/02C22C13/00C22C28/00H01L24/11H01L24/81H01L2224/0401H01L2224/05147H01L2224/13082H01L2224/13109H01L2224/13111H01L2224/13139H01L2224/13147H01L2224/16145H01L2224/16227H01L2224/81815H01L2924/014
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,831,210
App. No.
15/362,246
Granted
Nov 28, 2017
Kind
B2
Abstract

An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and provided along a boundary between the electrode and the solder. The joining layer including In and Ag prevents Cu—Sn alloy, such as Cu 6 Sn 5 , from being formed at the boundary between the electrode and the solder, and prevents generation of voids and cracks resulting from the Cu—Sn alloy. The electrode and the solder are joined with sufficient strength by the joining layer.

Claims (42)

1. An electronic device comprising:

an electrode including Cu;

a solder including Sn and provided above the electrode; and

a joining layer including In and Ag and provided along a boundary between the electrode and the solder, wherein

an average crystal grain diameter of the joining layer is smaller than an average crystal grain diameter of the solder.

2. The electronic device according to claim 1 , wherein

the joining layer includes alloy including In and Ag.

3. The electronic device according to claim 2 , wherein

the alloy includes AgIn 2 .

4. The electronic device according to claim 2 , wherein

the alloy includes AgIn 2 including Cu and Sn.

5. The electronic device according to claim 1 , wherein

the joining layer includes

a first alloy layer including Cu and Sn and provided on the electrode, and

a second alloy layer including In and Ag and provided on the first alloy layer.

6. The electronic device according to claim 5 , wherein

the first alloy layer is thinner than the second alloy layer.

7. The electronic device according to claim 5 , wherein

the first alloy layer includes Cu 6 Sn 5 or Cu 3 Sn.

8. The electronic device according to claim 5 , wherein

the first alloy layer includes Cu, Sn, and In.

9. The electronic device according to claim 5 , wherein

the second alloy layer includes AgIn 2 .

10. The electronic device according to claim 5 , wherein

the second alloy layer includes AgIn 2 including Cu and Sn.

11. The electronic device according to claim 1 , wherein

a melting point of the solder is 150° C. or less.

12. A production method of an electronic device, comprising:

forming solder including Sn above an electrode including Cu with a joining layer including In and Ag in-between, wherein

an average crystal grain diameter of the joining layer is smaller than an average crystal grain diameter of the solder.

13. The production method of the electronic device according to claim 12 , wherein

the forming includes:

forming material including Sn, In, Ag, and Cu on the electrode, and

forming the joining layer along a boundary between the electrode and the solder, by melting and solidifying the material on the electrode.

14. The production method of the electronic device according to claim 13 , wherein

the material includes Sn, 40 wt % to 65 wt % In, 0.01 wt % to 5 wt % Ag, and 0.01 wt % to 1 wt % Cu.

15. An electronic apparatus comprising:

an electronic device that includes

an electrode including Cu,

a solder including Sn and provided above the electrode, and

a joining layer including In and Ag and provided along a boundary between the electrode and the solder, wherein

an average crystal brain diameter of the joining layer is smaller than an average crystal grain diameter of the solder.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2016
From: UEMURA, TAIKI; SAKUYAMA, SEIKI
To: FUJITSU LIMITED
Reel/Frame 040695/0873 →
Priority Claims (1)
JP 2016-006043 · Jan 15, 2016 · national
Continuity (1)
Related Publication 20170207186A1 · Jul 20, 2017