Magnetic core inductor integrated with multilevel wiring network
An inductor is integrated into a multilevel wiring network of a semiconductor integrated circuit. The inductor includes a planar magnetic core and a conductive winding. The conductive winding turns around in generally spiral manner on the outside of the planar magnetic core. The conductive winding is piecewise constructed of wire segments and of VIAs. The wire segments pertain to at least two wiring planes and the VIAs are interconnecting the at least two wiring planes. Methods for such integration, and for fabricating laminated planar magnetic cores are also presented.
1. A structure, comprising:
a semiconductor integrated circuit comprising a multilevel wiring network disposed on a substrate; and
a first inductor integrated into said multilevel wiring network of said integrated circuit, said first inductor comprising a first planar magnetic core and a first conductive winding, said first conductive winding turned around said first planar magnetic core in a generally spiral manner;
a second inductor integrated into said multilevel wiring network of said integrated circuit, said second inductor comprising a second planar magnetic core and a second conductive winding, said second conductive winding turned around said second planar magnetic core in a generally spiral manner;
said first and second conductive windings further being electrically coupled to one another on one side of said inductors but not electrically coupled to one another on another side of said inductors,
said planar magnetic cores having a principal plane which is parallel with said respective wiring planes;
wherein at least one of the first and second planar magnetic cores has a laminated configuration comprising at least one layer of a magnetic material and at least one non-magnetic layer, said non-magnetic layer comprising current rectifying elements that prevent electrical current circulation in said planar magnetic cores perpendicularly to said principal plane.
2. The structure of claim 1 , wherein the rectifying elements suppress eddy currents in said at least one of the first and second planar magnetic cores.
3. The structure of claim 1 , wherein the rectifying elements include a Schottky diode.
4. The structure of claim 1 , wherein the rectifying elements include a semiconductor p-n junction.