System on a chip serial communication interface method and apparatus
A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.
1. A system-on-a-chip (SOC) comprising:
a processor block;
a read channel block;
a hard disk controller block; and
a first interface configured to communicate with a test unit via a second interface, wherein each of the test unit and the second interface is external to the SOC,
wherein based on a selection signal, the SOC is configured to operate, at a given time, in one of (i) a first mode that represents a normal operational mode of the SOC, (ii) a second mode that represents a processor mode for testing the SOC, (iii) a third mode that represents a hard disk controller mode for testing the SOC, or (iv) a fourth mode that represents a read channel only mode for testing the SOC,
wherein while the SOC operates in the first mode, (i) each of the processor block, the read channel block and the hard disk controller block are functional, and (ii) the SOC does not communicate with the test unit,
wherein while the SOC operates in the second mode, the processor block is configured to transmit data to the test unit via the first interface and the second interface,
wherein while the SOC operates in the third mode, (i) the read channel block is non-functional, and (ii) one or both of the processor block and the hard disk controller block is configured to transmit data to the test unit via the first interface and the second interface, and
wherein while the SOC operates in the fourth mode, (i) the read channel block is functional, (ii) the processor block and the hard disk controller block are non-functional, and (iii) the read channel block is configured to transmit data to the test unit via the first interface and the second interface.
2. The SOC of claim 1 , wherein the selection signal is received by the SOC from the test unit.
3. The SOC of claim 1 , wherein the first interface comprises:
a multiplexer configured to (i) receive data from each of the processor block, the read channel block, and the hard disk controller block, and (ii) based on a mode in which the SOC is operating, selectively output data from one of the processor block, the read channel block, and the hard disk controller block.
4. The SOC of claim 1 , wherein the first interface comprises:
a parallel-to-serial block configured to (i) based on the selection signal, receive parallel data from one of the processor, the hard disk controller block, or the read channel block, (ii) convert the parallel data to serial data, and (iii) transmit the serial data to the test unit via the second interface.
5. The SOC of claim 1 , wherein the first interface comprises:
a serial-to-parallel block configured to (i) receive serial data from the test unit via the second interface, (ii) convert the serial data to parallel data, and (iii) based on the selection signal, transmit the parallel data to one of the processor, the hard disk controller block, or the read channel block.
6. The SOC of claim 5 , wherein the first interface further comprises:
a delay module configured to (i) receive first data from the test unit via the second interface, (ii) based on the selection signal, transmit the first data to one of the processor, the hard disk controller block, or the read channel block, and (iii) subsequent to receiving the first data, delay the transmission of the first data to one of the processor, the hard disk controller block, or the read channel block by a delay amount.
7. The SOC of claim 6 , wherein the delay amount accounts for a time taken to convert the serial data to the parallel data by the serial-to-parallel block.
8. The SOC of claim 1 , further comprising:
one or more digital pins configured to transmit and receive signals,
wherein the selection signal is configured to alter a definition of the one or more digital pins.
9. The SOC of claim 1 , wherein:
the read channel block is a first read channel block;
while the SOC operates in the third mode, a second read channel block (i) is communicatively coupled to the SOC and (ii) mimics the operation of the non-functional first read channel block; and
the second read channel block is external to the SOC.
10. A method of operating a system-on-a-chip (SOC) comprising (i) a processor block, (ii) a read channel block, (iii) a hard disk controller block, and (iv) a first interface, the method comprising:
communicating, by the first interface, with a test unit via a second interface, wherein each of the test unit and the second interface is external to the SOC;
receiving, by the SOC, a selection signal;
based on the selection signal, receiving, by a parallel-to-serial block included in the first interface, parallel data from one of the processor, the hard disk controller block, or the read channel block;
converting, by the parallel-to-serial block, the parallel data to serial data; and
transmitting, by the parallel-to-serial block, the serial data to the test unit via the second interface; and
based on the selection signal, operating, by the SOC, at a given time, in one of (i) a first mode, (ii) a second mode, (iii) a third mode, or (iv) a fourth mode,
wherein while the SOC operates in the first mode, (i) each of the processor block, the read channel block and the hard disk controller block are functional, and (ii) the SOC does not communicate with the test unit,
wherein while the SOC operates in the second mode, the processor block is configured to transmit data to the test unit via the first interface and the second interface,
wherein while the SOC operates in the third mode, (i) the read channel block is non-functional, and (ii) one or both of the processor block and the hard disk controller block is configured to transmit data to the test unit via the first interface and the second interface, and
wherein while the SOC operates in the fourth mode, (i) the read channel block is functional, (ii) the processor block and the hard disk controller block are non-functional, and (iii) the read channel block is configured to transmit data to the test unit via the first interface and the second interface.
11. The method of claim 10 , wherein receiving the selection signal comprises:
receiving the selection signal from the test unit.
12. The method of claim 10 , wherein the read channel block is a first read channel block, and wherein the method further comprises:
while the SOC operates in the third mode, communicating, by the SOC, with a second read channel block that (i) mimics the operation of the non-functional first read channel block and (ii) is external to the SOC.
13. A method of operating a system-on-a-chip (SOC) comprising (i) a processor block, (ii) a read channel block, (iii) a hard disk controller block, and (iv) a first interface, the method comprising:
communicating, by the first interface, with a test unit via a second interface, wherein each of the test unit and the second interface is external to the SOC;
receiving, by the SOC, a selection signal;
receiving, by a serial-to-parallel block included in the first interface, serial data from the test unit via the second interface;
converting, by the serial-to-parallel block, the serial data to parallel data; and
based on the selection signal, transmitting, by the serial-to-parallel block, the parallel data to one of the processor, the hard disk controller block, or the read channel block; and
based on the selection signal, operating, by the SOC, at a given time, in one of (i) a first mode, (ii) a second mode, (iii) a third mode, or (iv) a fourth mode,
wherein while the SOC operates in the first mode, (i) each of the processor block, the read channel block and the hard disk controller block are functional, and (ii) the SOC does not communicate with the test unit,
wherein while the SOC operates in the second mode, the processor block is configured to transmit data to the test unit via the first interface and the second interface,
wherein while the SOC operates in the third mode, (i) the read channel block is non-functional, and (ii) one or both of the processor block and the hard disk controller block is configured to transmit data to the test unit via the first interface and the second interface, and
wherein while the SOC operates in the fourth mode, (i) the read channel block is functional, (ii) the processor block and the hard disk controller block are non-functional, and (iii) the read channel block is configured to transmit data to the test unit via the first interface and the second interface.
14. The method of claim 13 , further comprising:
receiving, by a delay module included in the first interface, first data from the test unit via the second interface;
based on the selection signal, transmitting, by the delay module, the first data to one of the processor, the hard disk controller block, or the read channel block; and
subsequent to receiving the first data, delaying, by the delay module, the transmission of the first data to one of the processor, the hard disk controller block, or the read channel block by a delay amount.
15. The method of claim 14 , wherein the delay amount accounts for a time taken to convert the serial data to the parallel data by the serial-to-parallel block.
16. The method of claim 13 , wherein the read channel block is a first read channel block, and wherein the method further comprises:
while the SOC operates in the third mode, communicating, by the SOC, with a second read channel block that (i) mimics the operation of the non-functional first read channel block and (ii) is external to the SOC.
17. The method of claim 13 , wherein:
the first mode is a normal operational mode of the SOC;
the second mode is a processor mode for testing the SOC;
the third mode is a hard disk controller mode for testing the SOC; and
the fourth mode is a read channel only mode for testing the SOC.
18. The method of claim 13 , wherein receiving the selection signal comprises:
receiving the selection signal from the test unit.
19. The method of claim 10 , wherein:
the first mode is a normal operational mode of the SOC;
the second mode is a processor mode for testing the SOC;
the third mode is a hard disk controller mode for testing the SOC; and
the fourth mode is a read channel only mode for testing the SOC.