Automatic architecture placement guidance
On-chip data transport network architectural units are assigned preferred placement locations based on architecture-level constraints. The preferred placement locations are used to generate placement constraints for a place and route tool. The placement constraints are applied to cells that are synthesized from each architectural unit. Constraints are blockages, fences, regions, and guides. Preferred placement locations are mapped to grid elements. Each grid elements defines a cell placement constraint.
1. A method of constraining placement of IP within a chip floorplan, the method comprising the steps:
synthesizing a plurality of units to generate a netlist, wherein the netlist represents the plurality of units to be placed within the chip floorplan and wherein each unit includes at least one cell;
defining a plurality of regions, wherein each region is a location for placement of at least one unit selected from the plurality of units;
determining an initial location, within a region selected from the plurality of regions, for at least one unit selected from the plurality of units;
generating at least one constraint to control the placement of the at least one unit;
passing the at least one constraint to a place and route tool; and
determining, using the place and route tool, a preferred location for at least one cell of the at least one unit within the region selected from the plurality of regions, based on the at least one constraint,
whereby the place and route tool determines the preferred location for the at least one cell of the at least one unit, such that the preferred location is within the region selected from the plurality of regions and meets the at least one constraint and optimizes the total length of wires connecting the cells of the plurality of units to the cells of other units of the netlist between the plurality of units,
wherein the preferred location and the optimized routing between the plurality of cells of the plurality of units can be used to create a physical design suitable for the manufacturing of a semiconductor device.
2. The method of claim 1 wherein the plurality of units are components of an on-chip data transport network.
3. The method of claim 1 wherein the plurality of units are components of a network-on-chip.
4. The method of claim 1 further comprising determining a set of grid elements that are part of a grid overlaid on the chip floorplan, wherein the preferred location is one grid element selected from the set of grid elements and the at least one constraint is specific to the one grid element.
5. The method of claim 1 wherein the at least one constraint is a distance between the plurality of units.
6. The method of claim 1 wherein the at least one constraint is a data transfer bandwidth.
7. The method of claim 1 wherein the at least one constraint is a timing path delay.
8. A method of constraining placement of IP within a chip floorplan, the method comprising the steps:
synthesizing a plurality of units to generate a netlist, wherein the netlist represents the plurality of units to be placed within the chip floorplan and wherein each unit includes at least one cell;
defining a plurality of regions, wherein each region is a location for placement of at least one unit selected from the plurality of units;
determining an initial location, within a region selected from the plurality of regions, for at least one unit selected from the plurality of units;
generating at least one constraint to control the placement of the at least one unit;
passing the at least one constraint to a place and route tool; and
determining, using the place and route tool, a preferred location for at least one cell of the at least one unit within the region selected from the plurality of regions, based on the at least one constraint,
whereby the place and route tool determines the preferred location for the at least one cell of the at least one unit, such that the preferred location is within the region selected from the plurality of regions and meets the at least one constraint and optimizes the total length of wires connecting the cells of the plurality of units to the cells of other units of the netlist between the plurality of units,
wherein the constraining placement of IP within the chip floorplan is implemented in fabricating semiconductor devices.
9. A method of constraining placement of IP within a chip floorplan, the method comprising the steps:
synthesizing a plurality of units to generate a netlist, wherein the netlist represents the plurality of units to be placed within the chip floorplan and wherein each unit includes at least one cell;
defining a plurality of regions, wherein each region is a location for placement of at least one unit selected from the plurality of units;
determining an initial location, within a region selected from the plurality of regions, for at least one unit selected from the plurality of units;
generating at least one constraint to control the placement of the at least one unit;
passing the at least one constraint to a place and route tool; and
determining, using the place and route tool, a preferred location for at least one cell of the at least one unit within the region selected from the plurality of regions, based on the at least one constraint,
whereby the place and route tool determines the preferred location for the at least one cell of the at least one unit, such that the preferred location is within the region selected from the plurality of regions and meets the at least one constraint and optimizes the total length of wires connecting the cells of the plurality of units to the cells of other units of the netlist between the plurality of units,
wherein the constraining placement of IP within the chip floor plan is implemented in manufacturing the chip.