Memory devices having common source lines including layers of different materials
A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate, a source area disposed on the substrate to extend in a first direction and including impurities, and a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials.
1. A memory device, comprising:
a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate;
a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate;
a source area disposed in the substrate to extend in a first direction and including impurities; and
a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials, wherein the common source line comprises:
a first layer disposed on the source area; and
a second layer disposed on the first layer and being thinner than the first layer,
wherein the second layer includes a barrier layer disposed on an upper surface of the first layer and a metal layer disposed on the barrier layer.
2. The memory device of claim 1 , wherein the first layer includes polysilicon doped with impurities; and
the second layer includes at least one of a metal, a metal silicide, and a metal compound.
3. The memory device of claim 1 , wherein the second layer extends longer than the first layer in the first direction.
4. The memory device of claim 1 :
wherein the first layer includes polysilicon doped with impurities having a same conductivity-type as the source area; and
wherein an impurity concentration of the first layer is higher than that of the source area.
5. The memory device of claim 1 :
wherein the common source line includes a third layer disposed on the second layer; and
wherein the third layer includes at least one of a metal, a metal silicide, and a metal compound.
6. The memory device of claim 5 , wherein the third layer has a greater thickness than the second layer.
7. The memory device of claim 5 , wherein the third layer extends longer than the first layer and the second layer in the first direction.
8. The memory device of claim 1 , further comprising an interlayer insulating layer disposed on the gate structure, wherein at least one of the plurality of layers included in the common source line is disposed on the interlayer insulating layer.
9. The memory device of claim 8 , wherein an upper surface of one of the plurality of layers included in the common source line is coplanar with an upper surface of the interlayer insulating layer.
10. The memory device of claim 1 , wherein a height of the common source line is greater than a height of the gate structure.
11. The memory device of claim 10 , further comprising a side spacer disposed between the common source line and the plurality of gate electrode layers to divide the gate structure into a plurality of parts.
12. A memory device, comprising:
a substrate;
a source area disposed in the substrate to extend in a first direction and including n-type impurities;
a plurality of channel areas extending in a direction perpendicular to an upper surface of the substrate;
a plurality of gate electrode layers stacked on the upper surface of the substrate and disposed to be adjacent to at least a portion of the plurality of channel areas; and
a common source line layer disposed on the source area to extend in the first direction, and including a first layer containing polysilicon having a higher concentration of n-type impurities than the source area and a second layer disposed on an upper surface of the first layer and containing at least one of a metal, a metal silicide, and a metal compound.
13. The memory device of claim 12 , wherein the second layer extends longer than the first layer in the first direction.
14. The memory device of claim 12 , further comprising:
a plurality of peripheral circuit devices disposed around the plurality of gate electrode layers;
a peripheral circuit contact connected to the plurality of peripheral circuit devices; and
a contact metal layer disposed on an upper surface of the peripheral circuit contact,
wherein an upper surface of the contact metal layer is coplanar with an upper surface of the second layer.
15. A vertical memory device comprising:
a gate structure including a plurality of gate electrodes stacked on a substrate;
a source area in the substrate, the source area extending in a first direction and including impurities; and
a common source line extending in a direction perpendicular to an upper surface of the substrate to be connected to the source area and including a plurality of layers containing different materials, wherein the common source line comprises:
a first layer disposed on the source area and including polysilicon doped with impurities; and
a second layer disposed on the first layer and including a barrier layer on an upper surface of the first layer and a metal layer on the barrier layer, wherein the second layer is thinner than the first layer and extends longer than the first layer in the first direction.
16. The device of claim 15 , wherein the second layer comprises a first metal layer including Titanium (Ti) and a second metal layer of tungsten (W) thereon.
17. The device of claim 15 , wherein a concentration of n-type impurities in the common source line is higher than a concentration of n-type impurities in the source area.