Sense amplifier scheme
View Patent ↗A sense amplifier circuit includes a pair of data lines, a pair of inverters, and a data line charging circuit. Each of the inverters is connected to a respective one of the data lines. The data line charging circuit includes a transistor. The transistor has a source/drain terminal connected to one of the data lines and a gate terminal connected to the other of the data lines.
1. A sense amplifier circuit comprising:
a pair of data lines;
a pair of inverters, each of which is connected to a respective one of the data lines;
a data line charging circuit including a first transistor having a source/drain terminal connected to one of the data lines and a gate terminal directly connected to the other of the data lines; and
a pre-charge circuit including a first transistor having a first source/drain terminal and a second source/drain terminal each of which is connected to an input of a respective one of the inverters and that are free from connection with the data lines.
2. The sense amplifier circuit of claim 1 , wherein the data line charging circuit further includes a second transistor having a source/drain terminal connected to the gate terminal of the first transistor and a gate terminal connected to the source/drain terminal of the first transistor.
3. The sense amplifier circuit of claim 1 , wherein the pre-charge circuit further includes a second transistor connected to the first source/drain terminal of the first transistor of the pre-charge circuit and free from connection with the data lines.
4. The sense amplifier circuit of claim 3 , wherein the pre-charge circuit further includes a third transistor connected to the second source/drain terminal of the first transistor of the pre-charge circuit and free from connection with the data lines.
5. The sense amplifier circuit of claim 1 , further comprising a first pass gate having a first source/drain terminal connected to the first source/drain terminal of the first transistor of the pre-charge circuit and a second source/drain terminal connected to the one of the data lines.
6. The sense amplifier circuit of claim 5 , further comprising a second pass gate having a first source/drain terminal connected to the second source/drain terminal of the first transistor of the pre-charge circuit and a second source/drain terminal connected to the other of the data lines.
7. The sense amplifier circuit of claim 1 , further comprising:
a pre-charge circuit including a transistor connected to the inverters; and
a sense amplifier enable circuit including a transistor connected to the inverters and free from connection with the transistor of the pre-charge circuit.
8. The sense amplifier circuit of claim 1 , further comprising a pair of circuits, each of which is connected between a respective one of the inverters and a respective one of the data lines, and each of which is configured to selectively couple the respective one of the inverters to the respective one of the data lines.
9. A memory comprising:
a pair of data lines;
a memory cell connected between the data lines;
a pair of inverters, each of which is connected to a respective one of the data lines;
a data line charging circuit including a first transistor having a source/drain terminal connected to one of the data lines and a gate terminal directly connected to the other of the data lines; and
a pre-charge circuit including a first transistor having a first source/drain terminal and a second source/drain terminal each of which is connected to an input of a respective one of the inverters and that are free from connection with the data lines.
10. The memory of claim 9 , wherein the data line charging circuit further includes a second transistor having a source/drain terminal connected to the gate terminal of the first transistor and a gate terminal connected to the source/drain terminal of the first transistor.
11. The memory of claim 9 , wherein the pre-charge circuit further includes a second transistor connected to the first source/drain terminal of the first transistor of the pre-charge circuit and free from connection with the data lines.
12. The memory of claim 11 , wherein the pre-charge circuit further includes a third transistor connected to the second source/drain terminal of the first transistor of the pre-charge circuit and free from connection with the data lines.
13. The memory of claim 9 , further comprising a first pass gate having a first source/drain terminal connected to the first source/drain terminal of the first transistor of the pre-charge circuit and a second source/drain terminal connected to the one of the data lines.
14. The memory of claim 13 , further comprising a second pass gate having a first source/drain terminal connected to the second source/drain terminal of the first transistor of the pre-charge circuit and a second source/drain terminal connected to the other of the data lines.
15. The memory of claim 9 , further comprising:
a pre-charge circuit including a transistor connected to the inverters; and
a sense amplifier enable circuit including a transistor connected to the inverters and free from connection with the transistor of the pre-charge circuit.
16. The memory of claim 9 , further comprising a pair of circuits, each of which is connected between a respective one of the inverters and a respective one of the data lines, and each of which is configured to selectively couple the respective one of the inverters to the respective one of the data lines.
17. A memory comprising:
a pair of data lines;
a memory cell connected between the data lines;
a pair of inverters, each of which includes a transistor that has a first source/drain terminal, a second source/drain terminal, and a gate terminal, the first source/drain terminal of the transistor of one of the inverters and the gate terminal of the transistor of the other of the inverters being directly connected to each other at a node, the second source/drain terminal of the transistor of the one of the inverters being connected to one of the data lines; and
a pre-charge circuit including a transistor connected to the node and free from connection with the data lines.
18. The memory of claim 17 , further comprising a data line charging circuit including a transistor having a source/drain terminal connected to the one of the data lines and a gate terminal connected to the other of the data lines.
19. The memory of claim 17 , further comprising a pass gate having a first source/drain terminal connected to the transistor of the pre-charge circuit and a second source/drain terminal connected to the one of the data lines.
20. The memory of claim 17 , further comprising:
a pre-charge circuit including a transistor connected to the inverters; and
a sense amplifier enable circuit including a transistor connected to the inverters and free from connection with the transistor of the pre-charge circuit.
21. The memory of claim 17 , further comprising a circuit connected between the second source/drain terminal of the transistor of the one of the inverters and the one of the data lines and configured to selectively couple the second source/drain terminal of the transistor of the one of the inverters to the one of the data lines.
22. The sense amplifier circuit of claim 1 , further comprising:
a pre-charge circuit including a transistor connected between inputs of the inverters; and
a pass gate having a first source/drain terminal connected to the transistor of the pre-charge circuit and a second source/drain terminal connected to one of the ata lines.