Memory device

1. A memory device comprising:

a memory array of memory cells arranged in rows and columns; and

responder signal circuitry to perform a calculation on a row of said memory array and generating a responder signal indicating that there is at least one cell in said row having a pre-defined value.

2. A memory device according to claim 1 wherein said responder signal circuitry comprises wired-OR circuitry.

3. A memory device according to claim 1 wherein said data candidate is arranged in a column of said memory array.

4. A memory device according to claim 1 wherein said memory cells are arranged in said columns in a NAND configuration.

5. A memory device according to claim 1 wherein said memory cells are arranged in said columns in a NOR configuration.

6. A memory device according to claim 1 wherein said responder signal circuitry performs Boolean OR operations on bit data in said memory array.

7. A memory device according to claim 1 wherein said responder signal circuitry communicates said responder signal to said memory array.

8. A memory device comprising:

a memory array of memory cells arranged in rows and columns; and

responder signal circuitry to generate a responder signal responsive to positive identification of a data candidate of said memory array,

wherein said responder signal circuitry communicates said responder signal to a global responder signal connecting to a plurality of memory arrays.

9. A memory device according to claim 1 wherein said memory cells comprises flash memory cells.

10. A method comprising:

selecting a data candidate having a maximum value from a plurality of data candidates stored in columns in a memory array, said selecting comprising, per at least one row of data in said memory array:

computing marker bit values for said row; and

performing a Boolean OR operation on said marker bit values to generate a responder signal value.

11. A method according to claim 10 further comprising performing a Boolean AND operation on said marker bit values and said data stored in said columns.

12. A method according to claim 10 further comprising initially setting said marker bit values to a predetermined value.

13. A method according to claim 10 further comprising selecting the data candidate when a marker bit value associated with the data candidate is different than a marker bit value of all other data candidates.

14. A method according to claim 10 further comprising performing Boolean OR operations on bit data in said memory array.

15. A method according to claim 10 further comprising communicating a responder signal to said memory array.

16. A method according to claim 10 further comprising connecting to a global responder signal connecting to a plurality of memory arrays.

17. A method according to claim 10 further comprising performing said computing in constant time.

18. A method according to claim 10 further comprising generating a responder signal responsive to positive identification of the data candidate in said memory array.

19. A method comprising:

selecting a data candidate having a maximum value from a plurality of data candidates stored in columns in a plurality of memory arrays, said selecting comprising, per at least one row of data per memory array:

computing marker bit values for said row of data in each of said plurality of memory arrays;

performing a Boolean OR operation on said marker bit values to generate a plurality of responder signal values, each responder signal value associated with a memory array of said plurality of memory arrays; and

transferring said plurality of responder signal values to a global responder signal connecting to said plurality of memory arrays.