Silicon carbide semiconductor device

1. A silicon carbide semiconductor device comprising, a laminated structure that includes a first conductive type semiconductor substrate, a first conductive type first silicon carbide semiconductor layer located on a main surface of the semiconductor substrate, and a first ohmic electrode located on a back surface of the semiconductor substrate, the laminated structure including a transistor region, a termination region, and a diode region, each region including a part of the semiconductor substrate, a part of the first silicon carbide semiconductor layer, and a part of the first ohmic electrode, wherein the termination region surrounds the transistor region and the diode region is located between the transistor region and the termination region when viewed in a direction perpendicular to the main surface of the semiconductor substrate,

wherein the transistor region includes a plurality of unit cell regions,

the silicon carbide semiconductor device comprises:

in each of the unit cell regions,

a second conductive type first well region located in a part of the first silicon carbide semiconductor layer;

a first conductive type source region located in the first well region;

a second silicon carbide semiconductor layer formed on a part of the first silicon carbide semiconductor layer so as to be in contact with at least a part of the first well region and a part of the source region, the second silicon carbide semiconductor layer including a first conductive type layer having a lower impurity concentration than an impurity concentration of at least the first silicon carbide semiconductor layer;

a gate insulating film on the second silicon carbide semiconductor layer;

a gate electrode located on the gate insulating film;

a second ohmic electrode electrically connected to the source region; and

an upper electrode electrically connected to the second ohmic electrode,

the silicon carbide semiconductor device comprises, in the diode region:

a second conductive type second well region located in a part of the first silicon carbide semiconductor layer;

a contact region located in the second well region and having a higher impurity concentration than an impurity concentration of the second well region;

a second silicon carbide semiconductor layer formed on a part of the first silicon carbide semiconductor layer so as to be in contact with at least a part of the contact region;

an insulating film formed on the second silicon carbide semiconductor layer and having a thickness substantially same as a thickness of the gate insulating film;

a gate electrode formed on at least a part of the insulating film;

a gate line located on the contact region and electrically connected to the gate electrode;

a gate pad located on the contact region and electrically connected to the gate line for establishing external connection;

an inner third ohmic electrode electrically connected to at least a region located between the gate line and the transistor region in the contact region, and an outer third ohmic electrode electrically connected to at least a region located between the gate line and the termination region in the contact region; and

a source line electrically connected to the inner third ohmic electrode and the upper electrode on each of the unit cell regions, and

the silicon carbide semiconductor device comprises, in the termination region,

a second conductive type impurity region located in a part of the first silicon carbide semiconductor layer,

wherein the gate electrode is located between the inner third ohmic electrode and the outer third ohmic electrode when viewed in a direction perpendicular to the main surface of the semiconductor substrate.

2. The silicon carbide semiconductor device according to claim 1 , further comprising, between the gate line in the diode region and the termination region, at least one unit cell having a structure same as a structure of each of the unit cell regions in the transistor region.

3. The silicon carbide semiconductor device according to claim 1 or 2 ,

wherein the laminated structure has a shape of a substantially rectangle as viewed in the direction, and

a breakdown voltage of the termination region on two corners closer to the gate pad out of four corners of the rectangle is higher than a breakdown voltage of the termination region on at least one of the other two corners.

4. The silicon carbide semiconductor device according to claim 3 ,

wherein the impurity region constitutes a field limiting ring (FLR) in the termination region, and

a radius of the impurity region on the two corners closer to the gate pad is larger than a radius of the impurity region on at least one of the other two corners.

5. The silicon carbide semiconductor device according to claim 3 ,

wherein the impurity region constitutes a field limiting ring (FLR) structure in the termination region, and

a width of the impurity region on the two corners closer to the gate pad is larger than a width of the impurity region on at least one of the other two corners.

6. The silicon carbide semiconductor device according to claim 1 , comprising a plurality of the third ohmic electrodes between the gate line in the diode region and the transistor region,

wherein the plurality of the third ohmic electrodes has a rectangular or a circular shape as viewed in the direction, and

a third ohmic electrode closest to a corner of the second well region, out of the plurality of the third ohmic electrodes, has an area larger than an area of a third ohmic electrode adjacent to the third ohmic electrode closest to the corner of the second well region.

7. The silicon carbide semiconductor device according to claim 1 , comprising a plurality of the third ohmic electrodes between the gate line in the diode region and the transistor region,

wherein the plurality of the third ohmic electrodes has a stripe shape as viewed in the direction, and

a width of the stripe is maximized at a corner of the second well region.

8. The silicon carbide semiconductor device according to claim 1 , wherein

the second well region is divided into multiple regions in the diode region, and

a space between the divided multiple second well regions is equal to or less than a space between the divided multiple second well regions and the first well region.