Reducing power consumption in a multi-slice computer processor
Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
1. A method of reducing power consumption in a multi-slice computer processor, the multi-slice computer processor including a re-order buffer, the method comprising:
designating an entry in the re-order buffer as being invalid and unwritten;
assigning a pending instruction to the entry in the re-order buffer;
responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid;
writing data generated by executing the pending instruction into the re-order buffer; and
responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
2. The method of claim 1 further comprising:
receiving a request to read the entry in the re-order buffer;
determining whether the entry in the re-order buffer is designated as being valid and written;
responsive to determining that the entry in the re-order buffer is designated as being valid and written, servicing the request to read the entry in the re-order buffer; and
responsive to determining that the entry in the re-order buffer is not designated as being valid and written, dismissing the request to read the entry in the re-order buffer.
3. The method of claim 1 , wherein the multi-slice processor further comprises an architected register file and the method further comprises:
receiving a request to read an entry in the architected register file;
determining whether the entry in the re-order buffer is designated as being valid;
responsive to determining that the entry in the re-order buffer is designated as being valid, dismissing the request to read the entry in the architected register file; and
responsive to determining that the entry in the re-order buffer is not designated as being valid, servicing the request to read the entry in the architected register file.
4. The method of claim 1 , wherein the multi-slice processor further comprises an architected register file and the method further comprises:
detecting that the pending instruction has executed; and
responsive to detecting that the pending instruction has executed, moving the entry in the re-order buffer to the architected register file.
5. The method of claim 4 further comprising, responsive to moving the entry in the re-order buffer to the architected register file, designating the entry in the re-order buffer as being invalid and unwritten.
6. The method of claim 1 , wherein the multi-slice processor further comprises an architected register file and the method further comprises:
dispatching the pending instruction, the pending instruction identifying an entry in the re-order buffer that includes an operand for the pending instruction;
determining whether the entry in the re-order buffer that includes the operand for the pending instruction is valid and written or invalid;
responsive to determining that the entry in the re-order buffer that includes the operand for the pending instruction is valid and written, reading the operand from the reorder buffer; and
responsive to determining that the entry in the re-order buffer that includes the operand for the pending instruction is invalid, reading the operand from the architected register file.
7. The method of claim 1 wherein each entry in the re-order buffer includes a valid bit and a reorder bit.