Information processing device including host device and semiconductor memory device having a block rearrangement to secure free blocks
A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
1. A semiconductor memory device capable of communicating with a host device, the host device having a first semiconductor memory, the semiconductor memory device comprising:
a second semiconductor memory having a plurality of blocks, the blocks including a first block, a second block and a third block, each of the blocks being a unit of an erase operation of the second semiconductor memory, the second semiconductor memory being nonvolatile; and
a controller circuit being capable of reading a valid first data from the first block and writing the first data to an area of the first semiconductor memory, the area having been designated by the host device for storing data from the semiconductor memory device, wherein:
the controller circuit is capable of reading a valid second data from the second block and writing the second data to the area of the first semiconductor memory; and
the controller circuit is capable of reading the first data and the second data from the area of the first semiconductor memory and writing the first data and the second data to the third block,
wherein when a block rearrangement to secure free blocks is executed in the semiconductor memory device, the controller circuit reads the valid first data from the first block, writes the first data to an area of the first semiconductor memory, reads the valid second data from the second block, writes the second data to the area of the first semiconductor memory, reads the first data and the second data from the area of the first semiconductor memory and writes the first data and the second data to the third block.
2. The semiconductor memory device according to claim 1 ,
wherein the block rearrangement includes a compaction process.
3. The semiconductor memory device according to claim 1 ,
wherein the block rearrangement includes a garbage collection process.
4. The semiconductor memory device according to claim 1 ,
wherein the block rearrangement includes a read-modify-write (RMW) process.
5. The semiconductor memory device according to claim 4 ,
wherein the controller circuit integrates the valid first data and the valid second data with write data received from the host device and writes the valid first data and the valid second data integrated with the write data to the third block in the RMW process.
6. The semiconductor memory device according to claim 1 ,
wherein the block rearrangement is executed when the number of the free blocks becomes smaller than a threshold value.
7. The semiconductor memory device according to claim 1 ,
wherein the controller uses a work area of the first semiconductor memory when the controller circuit reads the first data and the second data from the area of the first semiconductor memory and writes the first data and the second data to the third block.
8. The semiconductor memory device according to claim 1 , wherein the third block is a free block.
9. A memory system comprising:
a host device having a first semiconductor memory; and
a semiconductor memory device capable of communicating with the host device, the semiconductor memory device having:
a second semiconductor memory having a plurality of blocks, the blocks including a first block, a second block and a third block, each of the blocks being a unit of an erase operation of the second semiconductor memory, the second semiconductor memory being nonvolatile; and
a controller circuit being capable of reading a valid first data from the first block and writing the first data to an area of the first semiconductor memory, the area having been designated by the host device for storing data from the semiconductor memory device, wherein:
the controller circuit is capable of reading a valid second data from the second block and writing the second data to the area of the first semiconductor memory; and
the controller circuit is capable of reading the first data and the second data from the area of the first semiconductor memory and writing the first data and the second data to the third block,
wherein when a block rearrangement to secure free blocks is executed in the semiconductor memory device, the controller circuit reads the valid first data from the first block, writes the first data to an area of the first semiconductor memory, reads the valid second data from the second block, writes the second data to the area of the first semiconductor memory, reads the first data and second data from the area of the first semiconductor memory and writes the first data and the second data to the third block.
10. The memory system according to claim 9 , wherein the block rearrangement includes a compaction process.
11. The memory system according to claim 9 , wherein the block rearrangement includes a garbage collection process.
12. The memory system according to claim 9 , wherein the block rearrangement includes a read-modify-write (RMW) process.
13. The memory system according to claim 12 ,
wherein the controller circuit integrates the valid first data and the valid second data with write data received from the host device and writes the valid first data and the valid second data integrated with the write data to the third block in the RMW process.
14. The memory system according to claim 13 ,
wherein the block rearrangement is executed when the number of the free blocks becomes smaller than a threshold value.
15. The memory system according to claim 9 ,
wherein the controller uses a work area of the first semiconductor memory when the controller circuit reads the first data and the second data from the area of the first semiconductor memory and writes the first data and the second data to the third block.
16. The memory system according to claim 9 ,
wherein the host further comprises a DMA controller being capable of transferring the first data and the second data stored in the first semiconductor memory to the semiconductor memory system.
17. The memory system according to claim 9 ,
wherein the third block is a free block.