IP Library Granted Patent US 9,874,795
Granted Patent B2
US 9,874,795 · App. 14/372,395 · Granted Jan 23, 2018

Array substrate, manufacturing method, and display device thereof

Inventors: Hyun Sic Choi (Beijing, CN); Hui Li (Beijing, CN); Zhiqiang Xu (Beijing, CN); Yoon Sung Um (Beijing, CN)
Assignee: BOE Technology Group Co., Ltd.
G02F1/136209G02F1/1343G02F1/1368G02F1/133514G02F1/134309H01L27/124H01L27/1259H01L51/5262G02F2001/134372G02F2001/136222H01L27/3244
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Quick Facts
Patent No.
US 9,874,795
App. No.
14/372,395
Granted
Jan 23, 2018
Kind
B2
Abstract

An array substrate includes a substrate ( 10 ), a plurality of pixel regions ( 30 ) and a black matrix ( 15 ) separating the pixel regions ( 30 ) formed on the substrate ( 10 ); corresponding to a region where the black matrix ( 15 ) is located, the substrate ( 10 ) is provided with a thin film transistor. The pixel region ( 30 ) includes a first electrode ( 17 ) and a second electrode ( 20 ) configured for generating an electric field therebetween to drive liquid crystals. The second electrode ( 20 ) is disposed above the first electrode ( 17 ). The pixel region ( 30 ) further includes a color resist layer ( 16 ) disposed between a gate insulation layer ( 12 ) and the second electrode ( 20 ) and distributed in the pixel region ( 30 ). A method of manufacturing the array substrate and a display device are further disclosed.

Claims (26)

1. An array substrate, comprising: a substrate, a plurality of pixel regions and a black matrix separating the pixel regions formed on the substrate; corresponding to a region where the black matrix is located, the substrate is provided with a thin film transistor comprising a gate insulating layer; the pixel region comprises a first electrode and a second electrode configured for generating an electric field therebetween to drive liquid crystals, the second electrode is disposed above the first electrode, the pixel region further comprises:

a color resist layer disposed between the first electrode and the second electrode and distributed in the pixel region, and the color resist layer is in direct contact with the first electrode, and the first electrode is a pixel electrode, the second electrode is a common electrode which is connected to a common line formed in the same layer with a gate electrode layer;

wherein the thin film transistor further comprises a source and a drain electrode, the black matrix is disposed above the source and the drain electrode of the thin film transistor, the black matrix together with the first electrode completely overlay the thin film transistor, the black matrix is in direct contact with both the source electrode and the drain electrode between which an interval is provided, and the black matrix and the color resist layer are sequentially arranged in a direction parallel to the substrate, and the source electrode or the drain electrode, which is connected with the pixel electrode, comprises a portion which does not overlap both the black matrix and the color resist layer in a direction perpendicular to the substrate;

further comprising: a resin layer overlaying the black matrix, the color resist layer and the first electrode; a passivation layer overlaying the resin layer; the second electrode is disposed on the passivation layer.

2. The array substrate according to claim 1 , wherein the second electrode is a slit-shaped transparent electrode and disposed on the passivation layer.

3. The array substrate according to claim 1 , wherein the color resist layer comprises a plurality of primary color blocks, and the pixel region comprises a plurality of sub-pixel regions, each of the primary color blocks is distributed in one of the sub-pixel regions.

4. The array substrate according to claim 3 , further comprising:

a data line located in a same layer as the source and the drain electrode, wherein a position of the data line corresponds to a boundary region of any two of the primary color blocks in the color resist layer.

5. The array substrate according to claim 1 , wherein the thin film transistor further comprises a gate electrode, the array substrate further comprises:

a gate line disposed in the same layer as the gate electrode, the gate line being disposed in a shielding region of the black matrix.

6. A display device, comprising the array substrate according to claim 1 .

7. The array substrate according to claim 1 , wherein the color resist layer does not overlap the black matrix in the direction perpendicular to the substrate.

8. The array substrate according to claim 1 , wherein the thin film transistor further comprises a semiconductor layer, and the color resist layer does not overlap the semiconductor layer in the direction perpendicular to the substrate.

9. The array substrate according to claim 1 , wherein the black matrix does not overlap both the first electrode and the second electrode in the direction perpendicular to the substrate.

10. The array substrate according to claim 1 , wherein the black matrix does not overlap the pixel electrode in the direction perpendicular to the substrate.

11. The array substrate according to claim 1 , wherein both the entire first electrode and the entire second electrode are transparent.

12. The array substrate according to claim 1 , comprising a data line, wherein the data line does not overlap the black matrix in the direction perpendicular to the substrate.

13. An array substrate, comprising:

a substrate,

a plurality of pixel regions and a black matrix separating the pixel regions formed on the substrate;

wherein

corresponding to a region where the black matrix is located, the substrate is provided with a thin film transistor comprising a gate insulating layer;

the pixel region comprises a first electrode and a second electrode configured for generating an electric field therebetween to drive liquid crystals, the second electrode is disposed above the first electrode, and the first electrode is a pixel electrode, the second electrode is a common electrode which is connected to a common line formed in the same layer with a gate electrode layer;

the pixel region further comprises: a color resist layer disposed between the gate insulation layer and the second electrode and distributed in the pixel region, and a resin layer overlaying the black matrix, the color resist layer and the first electrode,

wherein the black matrix does not overlap both the first electrode and the second electrode in a direction perpendicular to the substrate.

14. The array substrate according to claim 13 , wherein the black matrix and the color resist layer are sequentially arranged in a direction parallel to the substrate, one of the first electrode and the second electrode is a pixel electrode, and the source electrode or the drain electrode, which is connected with the pixel electrode, comprises a portion which does not overlap both the black matrix and the color resist layer in the direction perpendicular to the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2014
From: CHOI, HYUN SIC; LI, HUI; XU, ZHIQIANG; UM, YOON SUNG
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 033316/0225 →
Priority Claims (1)
CN 2013 1 0210409 · May 30, 2013 · national
Continuity (1)
Related Publication 20150309377A1 · Oct 29, 2015