Sense amplifier and input/output circuit of semiconductor apparatus including the same

1. A sense amplifier comprising:

a first switch coupled between a first power supply terminal and any one of a first signal line pair;

a second switch coupled between the first power supply terminal and the other one of the first signal line pair;

a third switch configured to turn on the first switch by coupling a second power supply terminal to the first switch depending on a level of the any one of the first signal line pair; and

a fourth switch configured to turn on the second switch by coupling the second power supply terminal to the second switch depending on a level of the other one of the first signal line pair,

wherein the third and fourth switches are directly coupled to the second power supply terminal.

2. The sense amplifier of claim 1 , wherein the first signal line pair is a segment line pair coupled with a bit line pair.

3. The sense amplifier of claim 2 , wherein the sense amplifier is coupled between the segment line pair and a switching circuit for coupling the segment line pair and a local line pair.

4. The sense amplifier of claim 1 , wherein the first switch comprises a source coupled with any one of the first signal line pair, and a drain coupled with the first power supply terminal.

5. The sense amplifier of claim 4 , wherein the second switch comprises a source coupled with the other one of the first signal line pair, and a drain coupled with the first power supply terminal.

6. The sense amplifier of claim 4 , wherein the third switch comprises a gate coupled with the any one of the first signal line pair, a source coupled with a second power supply terminal, and a drain coupled with a gate of the first switch.

7. The sense amplifier of claim 4 , wherein the fourth switch comprises a gate coupled with the other one of the first signal line pair, a source coupled with a second power supply terminal, and a drain coupled with a gate of the second switch.

8. The sense amplifier of claim 1 , further comprising:

a fifth switch and a sixth switch configured for precharging gates of the first and second switches to predetermined levels according to a precharge signal.

9. The sense amplifier of claim 1 ,

wherein the first switch is configured by an N-type metal-oxide-semiconductor (NMOS) transistor, and

wherein the second switch is configured by an NMOS transistor.

10. An input/output circuit of a semiconductor apparatus, comprising:

a first sense amplifier configured to sense a voltage difference of a bit line pair;

a first switching circuit configured to couple the bit line pair and a segment line pair according to a first switching control signal; and

a second sense amplifier configured to perform amplification of a voltage difference of the segment line pair, in response to a level variation of the segment line pair according to a coupling of the bit line pair and the segment line pair,

wherein the second sense amplifier comprises:

a first switch comprising a source coupled with a segment line of the segment line pair, and a drain coupled with a ground terminal;

a second switch comprising a source coupled with a segment bar line of the segment line pair, and a drain coupled with the ground terminal;

a third switch comprising a gate coupled with the segment line, a source coupled with a power supply terminal, and a drain coupled with a gate of the first switch; and

a fourth switch comprising a gate coupled with the segment bar line, a source coupled with the power supply terminal, and a drain coupled with a gate of the second switch.

11. The input/output circuit of claim 10 , further comprising:

a precharge circuit configured to precharge the segment line pair to a predetermined level according to a segment precharge signal.

12. The input/output circuit of claim 11 , wherein the second sense amplifier is configured to precharge, according to the segment precharge signal, a control node related to the amplification of the voltage difference of the segment line pair, to a predetermined level.

13. The input/output circuit of claim 10 , further comprising:

a second switching circuit configured to couple the segment line pair and a local line pair according to a second switching control signal.

14. The input/output circuit of claim 10 , further comprising:

a fifth switch and a sixth switch configured for precharging the gates of the first and second switches to predetermined levels according to a segment precharge signal.