Impedance and swing control for voltage-mode driver
A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
1. A driver circuit, comprising:
a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node, each of the plurality of output circuits comprising:
a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output;
first source terminals of the pair of inverters coupled to the first common node; and
second source terminals of the pair of inverters coupled to the second common node;
a first voltage regulator having an output coupled to the first common node of the plurality of output circuits;
a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and
a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
2. The driver circuit of claim 1 , wherein the current compensation circuit comprises:
a plurality of circuits having an enable input, a first bias input, and a second bias input, each of the plurality of circuits having a first transistor, a second transistor, and a third transistor serially connected to provide a current path between the outputs of the first and second voltage regulators.
3. The driver circuit of claim 2 , wherein, for each of the plurality of circuits of the current compensation circuit, a gate of the first transistor is coupled to receive a signal of the enable input, a gate of the second transistor is coupled to receive a signal of the first bias input, and a gate of the third transistor is coupled to receive a signal of the second bias input.
4. The driver circuit of claim 1 , wherein the first voltage regulator comprises:
a first transistor coupled between a supply voltage source and the first common node of the plurality of outputs circuits; and
a first operational amplifier having a first input coupled to a first reference voltage source, a second input coupled to the first common node of the plurality of output circuits, and an output coupled to a gate of the first transistor.
5. The driver circuit of claim 4 , wherein the second voltage regulator comprises:
a second transistor coupled between a ground source and the second common node of the plurality of outputs circuits; and
a second operational amplifier having a first input coupled to a second reference voltage source, a second input coupled to the second common node of the plurality of output circuits, and an output coupled to a gate of the second transistor.
6. The driver circuit of claim 1 , further comprising:
a first capacitor coupled between the first common node of the plurality of output circuits and a ground source; and
a second capacitor coupled between the second common node of the plurality of output circuits and the ground source.
7. The driver circuit of claim 1 , wherein the differential output of the plurality of output circuits is coupled to a pair of transmission lines.
8. A method of controlling a driver circuit in a transmitter, comprising:
receiving a plurality of outputs of an equalizer in the transmitter;
coupling each of the plurality of outputs of the equalizer to at least one of a plurality of output circuits of the driver circuit;
enabling first and second voltage regulators coupled to the plurality of output circuits; and
enabling at least one of a plurality of current compensation circuits coupled between the first and second voltage regulators;
wherein the plurality of output circuits is coupled in parallel between a differential input and a differential output and includes a first common node and a second common node, wherein each of the plurality of output circuits comprises a series combination of a pair of enable circuits, a pair of inverters, and a pair of resistors, coupled between the differential input and the differential output; a first transistor coupled between the first common node and first source terminals of the pair of inverters; and a second transistor coupled between the second common node and second source terminals of the air of inverters, and wherein the method further comprises:
disabling at least one of the plurality of output circuits; and
adjusting a gate-to-source voltage of each of the first transistor and the second transistor in each of the plurality of circuits based on feedback from first and second replica output circuits.