Metal line connection for improved RRAM reliability, semiconductor arrangement comprising the same, and manufacture thereof
Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.
1. An integrated circuit (IC) device comprising:
a substrate;
a plurality of metal interconnect layers disposed over the substrate;
a top electrode and a bottom electrode which are separated from one another by a dielectric layer and which are located above the substrate between two of the plurality of metal interconnect layers;
a first metal line located in a first metal interconnect layer and connected to the bottom electrode, wherein the first metal line has a first cross-sectional area; and
a second metal line located in a second metal interconnect layer that is higher above the substrate than the first metal interconnect layer, wherein the second metal line has a second cross-sectional area greater than the first cross-sectional area.
2. The IC device of claim 1 , wherein the second metal interconnect layer is higher above the substrate than the top electrode.
3. The IC device of claim 2 , wherein the first metal interconnect layer is closer to the substrate than the bottom electrode.
4. The IC device of claim 1 , wherein the second cross-sectional area ranges from 1.1 times the first cross-sectional area to 10 times the first cross-sectional area.
5. The IC device of claim 1 , wherein top electrode, bottom electrode, and dielectric layer correspond to a memory cell; wherein the first metal line corresponds to a wordline of the memory cell and the second metal line corresponds to a bitline of the memory cell; and the second cross-sectional area is between two times and six times the first cross-sectional area.
6. The IC device of claim 1 , wherein top electrode, bottom electrode, and dielectric layer correspond to a memory cell; wherein the first metal line corresponds to a sourceline of the memory cell and the second metal line corresponds to a bitline of the memory cell; and the second cross-sectional area is between 1.1 times and 1.8 times the first cross-sectional area.
7. The IC device of claim 1 , wherein top electrode, bottom electrode, and dielectric layer correspond to a memory cell; where the first metal line corresponds to a wordline of the memory cell and the second metal line corresponds to a sourceline of the memory cell; and the second cross-sectional area is between 2.2 times and 10 times the first cross-sectional area.
8. The IC device of claim 1 , wherein the two of the plurality of metal interconnect layers include a lower metal interconnect layer under the bottom electrode and an upper metal interconnect layer above the top electrode, further comprising:
a dielectric etch stop layer located above the lower metal interconnect layer;
a diffusion barrier layer having a peripheral portion located above the dielectric etch stop layer and having a central region which is recessed relative to the peripheral portion and which extends downward through an opening in the dielectric etch stop layer to contact the lower metal interconnect layer; and
wherein the bottom electrode is u-shaped and conformally overlies the diffusion barrier layer.
9. The IC device of claim 8 :
wherein the dielectric layer conformally overlies the bottom electrode and has outermost dielectric layer sidewalls which are spaced apart by a first distance;
wherein the top electrode conformally overlies the dielectric layer and has outermost top electrode sidewalls which are spaced apart by a second distance, the second distance being less than the first distance; and further comprising:
a sidewall spacer structure located along the outermost top electrode sidewalls and over outer edge regions of the dielectric layer, the sidewall spacer structure having outermost spacer sidewalls which are aligned to the outermost dielectric layer sidewalls.
10. An integrated circuit (IC) device comprising:
a substrate;
a plurality of metal interconnect layers disposed at a plurality of different heights, respectively, over the substrate;
a first metal line located in a first of the plurality of metal interconnect layers, wherein the first metal line has a first cross-sectional area; and
a second metal line located in a second of the plurality of metal interconnect layers that is higher above the substrate than the first metal interconnect layer, wherein the second metal line has a second cross-sectional area greater than the first cross-sectional area.
11. The IC device of claim 10 , wherein the second cross-sectional area is between two times and six times the first cross-sectional area.
12. The IC device of claim 10 , wherein the second cross-sectional area is between 1.1 times and 1.8 times the first cross-sectional area.
13. The IC device of claim 10 , wherein the second cross-sectional area is between 2.2 times and 10 times the first cross-sectional area.
14. The IC device of claim 10 :
wherein the first metal line has a first thickness, as measured along a first axis that is perpendicular to an upper surface of the substrate, and has a first width, as measured along a second axis that is co-planar with an upper surface of the substrate; and
wherein the second metal line has a second thickness, as measured along the first axis, and has a second width, as measured along the second axis, the second thickness being greater than the first thickness and the second width being greater than the first width.
15. The IC device of claim 14 , wherein the second thickness ranges from 1.1 times and 3.0 times the first thickness, and the second width ranges from 1.1 to 4.0 times the first width.
16. An integrated circuit (IC) device comprising:
a substrate;
a plurality of metal interconnect layers disposed over the substrate;
a memory cell disposed above the substrate between two of the plurality of metal interconnect layers, wherein the memory cell comprises a top electrode, a bottom electrode, and a dielectric layer separating the top electrode and the bottom electrode;
a first metal line located in a first metal interconnect layer and connected to the bottom electrode of the memory cell, wherein the first metal line has a first cross-sectional area; and
a second metal line located in a second metal interconnect layer that is higher above the substrate than the first metal interconnect layer and having a second cross-sectional area ranging from 1.1 times the first cross-sectional area to 10 times the first cross-sectional area.
17. The IC device of claim 16 , wherein the memory cell is a resistive random access memory (RRAM) cell.
18. The IC device of claim 16 , wherein the two of the plurality of metal interconnect layers include a lower metal interconnect layer under the bottom electrode and an upper metal interconnect layer above the top electrode, further comprising:
a dielectric etch stop layer located above the lower metal interconnect layer;
a diffusion barrier layer having a peripheral portion located above the dielectric etch stop layer and having a central region which is recessed relative to the peripheral portion and which extends downward through an opening in the dielectric etch stop layer to contact the lower metal interconnect layer; and
wherein the bottom electrode is u-shaped and conformally overlies the diffusion barrier layer.
19. The IC device of claim 18 :
wherein the dielectric layer conformally overlies the bottom electrode and has outermost dielectric layer sidewalls which are spaced apart by a first distance;
wherein the top electrode conformally overlies the dielectric layer and has outermost top electrode sidewalls which are spaced apart by a second distance, the second distance being less than the first distance; and further comprising:
a sidewall spacer structure located along the outermost top electrode sidewalls and over outer edge regions of the dielectric layer, the sidewall spacer structure having outermost spacer sidewalls which are aligned to the outermost dielectric layer sidewalls.
20. The IC device of claim 19 , wherein the top electrode includes a central region that is recessed relative to a peripheral region of the top electrode, with inner sidewalls of the top electrode connecting the central region and peripheral region of the top electrode; and further comprising:
a via extending downward from the upper metal interconnect layer and having via outer sidewalls that contact the inner sidewalls of the top electrode.