III-nitride based N polar vertical tunnel transistor
View Patent ↗A semiconductor structure, device, or N-polar III-nitride vertical field effect transistor. The structure, device, or transistor includes a current blocking layer and an aperture region. The current blocking layer and aperture region are comprised of the same material. The current blocking layer and aperture region are formed by polarization engineering and not doping or implantation. A method of making a semiconductor structure, device, or III-nitride vertical transistor. The method includes obtaining, growing, or forming a functional bilayer comprising a barrier layer and a two-dimensional electron gas-containing layer. The functional bilayer is not formed via a regrowth step.
1. A semiconductor device comprising:
a drain;
a barrier layer disposed on a first side of the drain and in electronic communication with the drain, the barrier layer comprising a current blocking layer and an aperture region;
a two-dimensional electron gas-containing layer disposed on the first side relative to the barrier layer;
a gate electrode oriented to alter the energy levels of the aperture region when a gate voltage is applied to the gate electrode; and
a source in ohmic contact with the two-dimensional electron gas-containing layer,
wherein the current blocking layer and aperture region are formed by polarization engineering and not doping or implantation, and the device has a resistance in an OFF-state of at least about 1000 Ω·cm 2 .
2. The semiconductor device of claim 1 , the two-dimensional electron gas-containing layer comprising a two-dimensional electron gas, wherein the two-dimensional electron gas has an electron density of about 1×10 12 cm −2 to about 2.5×10 13 cm −2 .
3. The semiconductor device of claim 1 , wherein the aperture region has an electron mobility of about 300 cm 2 /V·s to about 2200 cm 2 /V·s when the gate voltage applied to the gate electrode exceeds a threshold voltage.
4. The semiconductor device of claim 1 , wherein the barrier layer has a thickness of about 1 nm to about 20 nm.
5. The semiconductor device of claim 1 , wherein the current blocking layer and aperture region are comprised of the same material.
6. The semiconductor device of claim 1 , further comprising a current spreading layer and a drift layer disposed between the drain and the barrier layer, the drift layer disposed on the first side relative to the current spreading layer.
7. The semiconductor device of claim 1 , wherein the semiconductor device is a depletion mode device.
8. The semiconductor device of claim 1 , wherein the semiconductor device is an enhancement mode device.
9. The semiconductor device of claim 1 , wherein the barrier layer comprises AlGaN, (Al,In,Ga)N, or a combination thereof.
10. The semiconductor device of claim 1 , wherein the two-dimensional electron gas-containing layer comprises GaN, (Al,In,Ga)N, or a combination thereof.
11. The semiconductor device of claim 1 , wherein the device has a resistance in the ON-state of at most about 10 mΩ·cm 2 .
12. The semiconductor device of claim 1 , wherein the device has an On/Off current ratio of 10 2 to 10 10 .
13. The semiconductor device of claim 1 , wherein the device has a current density of less than about 0.4 A/cm 2 in an OFF state.
14. The semiconductor device of claim 1 , further comprising a substrate in contact with the drain.
15. A method of making a semiconductor device, the method comprising:
obtaining, growing, or forming a N-polar GaN substrate comprising a functional bilayer comprising a barrier layer and a two-dimensional electron gas-containing layer disposed on a first side of the barrier layer;
removing a portion of the functional bilayer to form a gate region;
depositing a dielectric material in the gate region and atop the two-dimensional electron gas-containing layer on the first side relative to the two-dimensional electron gas-containing layer;
removing two portions of the dielectric material atop the two-dimensional electron gas-containing layer to form source regions;
forming source electrodes in ohmic contact with the two-dimensional electron gas-containing layer in the source regions;
forming a gate electrode atop the dielectric material in the gate region; and
forming a drain disposed on a second side opposite the first side of the functional bilayer,
wherein the method is performed without a regrowth step.
16. The method of claim 15 , wherein the N-polar GaN substrate includes a drift layer disposed on the second side relative to the barrier layer and a current spreading layer disposed on the second side relative to the drift layer, wherein the drain is disposed on the second side relative to the current spreading layer.
17. The method of claim 15 , the method comprising growing the N-polar GaN substrate is grown in a single crystal growth process.
18. The method of claim 15 , wherein the gate region extends throughout the two-dimensional gas-containing layer and the barrier layer.
19. A method of making a semiconductor device, the method comprising:
obtaining, growing, or forming a N-polar GaN substrate comprising functional bilayer comprising a barrier layer and a two-dimensional electron gas-containing layer disposed on a first side of the barrier layer;
forming a source electrode in ohmic contact with the two-dimensional electron gas-containing layer;
forming a gate electrode oriented to provide alter the energy levels of the barrier layer to form an aperture region when a gate voltage is applied exceeding a threshold voltage; and
forming a drain disposed on a second side of the barrier layer, the second side opposite the first side,
wherein the method is performed without a regrowth step.