Method for reducing contact resistance in semiconductor structures
Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.
1. A structure comprising;
a fin over a substrate;
a gate structure, on the fin, having a sidewall;
a sidewall spacer adjacent to the sidewall;
a source/drain (S/D) region adjacent to the sidewall spacer; and
a layer of doped crystalline material disposed on the S/D region, wherein the layer of doped crystalline material comprises a higher doping concentration than a doping concentration of the S/D region.
2. The structure of claim 1 , wherein the layer of doped crystalline material is disposed in the fin.
3. The structure of claim 1 , wherein the layer of doped crystalline material comprises a layer of doped crystalline semiconductor material.
4. The structure of claim 3 , wherein the layer of doped crystalline semiconductor material comprises a layer of n-doped crystalline silicon with a doping concentration in a range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .
5. The structure of claim 3 , wherein the layer of doped crystalline semiconductor material comprises at least one of a layer of n-doped crystalline silicon and a layer of n-doped crystalline germanium.
6. The structure of claim 3 , wherein the layer of doped crystalline semiconductor material comprises a layer of n-doped crystalline silicon germanium with a doping concentration in a range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .
7. The structure of claim 1 , further comprising a contact layer formed on the layer of doped crystalline material.
8. The structure of claim 1 , wherein a thickness of the layer of doped crystalline material is in a range of about 1 nm to about 10 nm.
9. The structure of claim 1 , wherein the doped crystalline material and a material of the S/D region have a same crystal orientation.
10. The structure of claim 1 , wherein the doped crystalline material and a material of the S/D region are formed of same elements.
11. The structure of claim 1 , wherein the doped crystalline material is different from a material of the S/D region.
12. The structure of claim 7 , wherein the contact layer comprises a silicide layer.
13. A structure comprising;
a fin, over a substrate, having a top surface and a pair of opposing side surfaces;
a gate structure, on the fin, having a sidewall;
a sidewall spacer adjacent to the sidewall;
a source/drain (S/D) region in the fin and adjacent to the sidewall spacer, a portion of the source/drain (S/D) region being disposed in the fin; and
a layer of doped crystalline material on the S/D region and formed on the side surface of the fin, wherein the layer of doped crystalline material comprises a higher doping concentration than a doping concentration of the S/D region.
14. The structure of claim 13 , wherein the layer of doped crystalline material comprises a layer of n-doped crystalline silicon with a doping concentration in a range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .
15. The structure of claim 13 , wherein the layer of doped crystalline material comprises a layer of n-doped crystalline silicon germanium with a doping concentration in a range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .
16. The structure of claim 13 , wherein a thickness of the layer of doped crystalline material is in a range of about 1 nm to about 10 nm.
17. A semiconductor structure comprising:
a fin on a substrate;
a first gate structure, over the fin, with a first sidewall and a first spacer formed thereon;
a second gate structure, over the fin, with a second sidewall and a second spacer formed thereon, the second spacer opposing the first spacer;
a crystalline source/drain (S/D) region formed in the fin and between the first spacer and the second spacer; and
a crystalline layer formed on the crystalline S/D region, wherein the crystalline layer comprises a higher doping concentration than a doping concentration of the crystalline S/D region.
18. The semiconductor structure of claim 17 , wherein a thickness of the crystalline layer is in a range of about 1 nm to about 10 nm.
19. The semiconductor structure of claim 17 , wherein the crystalline layer comprises an n-doped crystalline silicon layer with a doping concentration in a range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .
20. The semiconductor structure of claim 17 , wherein the crystalline layer comprises an n-doped crystalline silicon germanium layer with a doping concentration in a range of about 5×10 20 atoms/cm 3 to about 7×10 21 atoms/cm 3 .