Method and apparatus to configure thermal design power in a microprocessor
A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.
1. A system comprising:
a processor comprising a plurality of cores;
a storage controller to communicatively couple the processor to a storage device;
wherein the processor comprises:
an integrated memory controller to communicatively couple the processor to a system memory;
first hardware logic to set a thermal design power (TDP) setting for the processor in a Basic Input/Output System (BIOS) based on a user selection in a user interface and to change a configurable power limit value for the processor based on the TDP setting, wherein the configurable power limit value is to limit a power consumption of the processor,
second hardware logic to read the configurable power limit value and write, in a register of a first core, power state information associated with the configurable power limit value, the power state information including a maximum power state for the first core and indicating one of a plurality of power states in which the first core is to currently operate,
wherein the plurality of power states includes at least one low power state and at least one turbo mode state;
a level one cache integral to each one of the plurality of cores;
a first shared cache shared by two or more of the plurality of cores; and
an inter-processor interconnect to communicatively couple the processor to one or more other processors; and
a second shared cache external to the processor and communicatively coupled to one or more of the processors.
2. The system of claim 1 , wherein the processor comprises a plurality of core-level caches including the level one cache.
3. The system of claim 1 comprising an input/output unit.
4. The system of claim 1 wherein the processor and the one or more other processors include a common processor architecture.
5. A system comprising:
processing means comprising a plurality of cores;
system memory operably coupled to the processing means;
a storage controlling means operably coupled to the processing means; and
integrated memory controller means to communicatively couple the processor to a system memory;
first logic means to set a thermal design power (TDP) setting in a Basic Input/Output System (BIOS) based on a user selection in a user interface for the processor and to change a configurable power limit value for the processor based on the TDP setting, wherein the configurable power limit value is to limit a power consumption of the processor,
second logic means to read the configurable power limit value and write, in a register of a first core, power state information associated with the configurable power limit value, the power state information including a maximum power state for the first core and indicating one of a plurality of power states in which the first core is to currently operate,
wherein the plurality of power states includes at least one low power state and at least one turbo mode state;
a level one cache integral to each one of the plurality of cores;
a first shared cache shared by two or more of the plurality of cores; and
inter-processor interconnect means to communicatively couple the processing means to one or more other processing means; and
a second shared cache external to the processing means and communicatively coupled to the processing means.
6. The system of claim 5 wherein the processing means comprises a plurality of core-level caches including the level one cache.
7. The system of claim 5 , comprising an input/output means.
8. The system of claim 5 , wherein the processing means and the one or more other processing means include a common processor architecture.