Semiconductor chip test device
A semiconductor chip test device may include: a guide plate having a seating groove formed at the bottom thereof; a substrate coupled to the bottom of the guide plate, and having an upper semiconductor chip mounted on the top surface thereof such that the upper semiconductor chip is positioned in the seating groove; an upper socket having upper pogo pins coupled to the bottom of the guide plate in a state where the upper pogo pins are in contact with bottom patterns of the substrate, and having lower pogo pins formed on the bottom surface thereof, wherein the upper pogo pins protrude upward, and the lower pogo pins protrude downward; and a lower socket having a lower semiconductor chip seated on the top surface thereof, the lower semiconductor chip being in contact with the lower pogo pins.
1. A semiconductor chip test device comprising:
a guide plate having a seating groove formed at the bottom thereof;
a substrate coupled to the bottom of the guide plate, and having an upper semiconductor chip mounted on the top surface thereof such that the upper semiconductor chip is positioned in the seating groove;
an upper socket coupled to the bottom of the substrate, and having
upper pogo pins formed on the top surface thereof and contacted with bottom patterns of the substrate, and
lower pogo pins formed on the bottom surface thereof,
wherein the upper pogo pins protrude upward, and the lower pogo pins protrude downward; and
a lower socket having a lower semiconductor chip seated on the top surface thereof, the lower semiconductor chip being in contact with the lower pogo pins,
wherein the guide plate has an opening/closing groove formed at the top thereof, the opening/closing groove communicating with the seating groove while being formed through the guide plate in the vertical direction, and a pressurizing member is installed in the opening/closing groove so as to elastically support the upper semiconductor chip positioned in the seating groove downward.
2. The semiconductor chip test device of claim 1 , wherein the pressurizing member comprises:
a cover coupled to the opening/closing groove; and
a pressurizing part positioned between the cover and the upper semiconductor chip, and electrically supporting the upper semiconductor chip downward.
3. The semiconductor chip test device of claim 2 , wherein the pressurizing part comprises:
a pressurizing plate installed between the cover and the upper semiconductor chip so as to be lifted and lowered, and pressurizing the upper semiconductor chip downward; and
an elastic member installed between the cover and the pressurizing plate and providing an elastic force of pressurizing the pressurizing plate downward.
4. The semiconductor chip test device of claim 3 , wherein the pressurizing plate comprises a plurality of installation grooves formed at the center position thereof, which forms the same line as the center of the upper semiconductor chip, and at the edge part around the center position thereof, the installation grooves being formed at even intervals along the edge part.
5. The semiconductor chip test device of claim 1 , further comprising a fastening member coupling the upper socket and the substrate to the bottom of the guide plate through edge parts of the upper socket and the substrate.
6. The semiconductor chip test device of claim 1 , wherein the upper pogo pins and the lower pogo pins are arranged in a plurality of lines along the top and bottom edges of the upper socket.
7. The semiconductor chip test device of claim 1 , wherein
the upper socket has a plurality of arrangement pins formed at the bottom edge thereof so as to protrude downward, and
the lower socket has a plurality of concave insertion grooves formed on the top surface thereof, such that the arrangement pins are inserted into the insertion grooves.