IP Library Granted Patent US 9,911,577
Granted Patent B2
US 9,911,577 · App. 15/236,319 · Granted Mar 6, 2018

Arrangement for plasma processing system control based on RF voltage

Inventors: John C. Valcore, Jr. (Berkeley, CA); Henry S. Povolny (Newark, CA)
Assignee: Lam Research Corporation
H01J37/32137G05B15/02G05B19/418H01J37/32082H01J37/3299H01J37/32174H01J37/32183H01J37/32917H01J37/32926G05B2219/45031
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Quick Facts
Patent No.
US 9,911,577
App. No.
15/236,319
Filed
Aug 12, 2016
Granted
Mar 6, 2018
Kind
B2
Art Unit
2819
USPC
438/11
Abstract

An arrangement for controlling a plasma processing system is provided. The arrangement includes an RF sensing mechanism for obtaining an RF voltage signal. The arrangement also includes a voltage probe coupled to the RF sensing mechanism to facilitate acquisition of the signal while reducing perturbation of RF power driving a plasma in the plasma processing system. The arrangement further includes a signal processing arrangement configured for receiving the signal, split the voltage signals into a plurality of channels, convert the signals into a plurality of direct current (DC) signals, convert the DC signals into digital signals and process the digital signal in a digital domain to generate a transfer function output. The arrangement moreover includes an ESC power supply subsystem configured to receive the transfer function output as a feedback signal to control the plasma processing system.

Claims (18)

1. A system, comprising:

a radio frequency (RF) sensing mechanism, said RF sensing mechanism is proximate to a component of an electrostatic chuck (ESC) to obtain an RF voltage signal, the ESC being disposed within the system that is used for plasma processing, wherein the component of the ESC is outside a region exposed to plasma, when plasma is formed within the system;

a voltage probe coupled to said RF sensing mechanism to facilitate acquisition of said RF voltage signal while reducing perturbation of RF power driving a plasma in the system;

a signal processing arrangement including,

an anti-aliasing filter to filter RF voltage signal received from the voltage probe;

a RF splitter to split the filtered RF voltage signal into a plurality of channels and to convert the RF voltage signal for each of the plurality of channels into a corresponding direct current (DC) signal, wherein one of the plurality of channels is maintained by the RF splitter as an unfiltered broadband version of the RF voltage signal;

an analog-to-digital converter (ADC) to convert the DC signal of each of the plurality of channels to a corresponding digital signal;

a digital processing block to process the digital signals by filtering the digital signals and computing a transfer function using the digital signals that were filtered as input to generate a transfer function output, the transfer function output accounting for contribution of frequency of each of the plurality of channels of the RF voltage signal including the unfiltered broadband version of the RF voltage signal in deriving wafer potential; and

an ESC power supply subsystem to receive said transfer function output as a feedback signal to control plasma processing within the system.

2. The system of claim 1 , wherein the filtering by the digital processing block includes detecting a peak voltage of each frequency in the plurality of channels including the peak voltage of the corresponding frequency of the unfiltered broadband version of the RF voltage signal,

wherein detecting a peak voltage includes detecting a positive peak voltage, a negative peak voltage, or a combination of both positive peak voltage and negative peak voltage.

3. The system of claim 1 , wherein the voltage probe is implemented at least by a capacitor divider network.

4. The system of claim 1 , wherein a filter frequency of the anti-aliasing filter is set to half of a sampling rate of the ADC.

5. The system of claim 1 , wherein the digital processing block uses a field programmable gate array (FPGA) to process the digital signals.

6. The system of claim 1 , wherein computing the transfer function further includes using at least one plasma processing chamber parameter as input to generate the transfer function output that affects wafer potential.

7. The system of claim 6 , wherein the plasma processing chamber parameter includes at least one of chamber pressure, chamber gap defined by distance between electrodes, RF delivered power, RF frequency, RF generator impedance matching network tap positions having capacitor positions of variable inductance-capacitance (LC) network, chamber chemistry, chamber topology including a ground area ratio, wafer type, and wafer resistivity.

8. The system of claim 1 , wherein the transfer function represents a linear transfer function obtained using a multi-variate analysis.

9. The system of claim 1 , wherein the transfer function represents a non-linear transfer function obtained using a power equation.

Continuity (7)
Division 14808846 · Jul 24, 2015
Continuation 13959584 · Aug 5, 2013
Continuation 12962524 · Dec 7, 2010
Continuation In Part 12950710 · Nov 19, 2010
Provisional Application 61303628 · Feb 11, 2010
Provisional Application 61262886 · Nov 19, 2009
Related Publication 20160351375A1 · Dec 1, 2016