Vertical fin field effect transistor with air gap spacers

1. A method of forming a fin field effect transistor device with air gaps, comprising:

forming one or more vertical fins on a substrate;

forming a source/drain layer on the substrate in contact with the one or more vertical fins on a substrate;

forming a sacrificial bottom spacer on the source/drain layer;

forming a sacrificial spacer cap on the sacrificial bottom spacer;

forming a gate dielectric layer on at least a portion of the one or more vertical fins and the sacrificial spacer cap;

forming a gate electrode on the gate dielectric layer;

forming a U-shaped trough on the gate electrode;

forming a sacrificial top spacer fill in the U-shaped trough; and

removing the sacrificial bottom spacer to form a bottom void space between the source/drain layer and the sacrificial spacer cap.

2. The method of claim 1 , wherein the sacrificial bottom spacer is silicon-germanium (Si x Ge 1-x ), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), amorphous carbon (a-C), or combinations thereof.

3. The method of claim 1 , wherein the sacrificial top spacer fill is silicon nitride (SiN), amorphous carbon (a-C), amorphous silicon (a-Si), silicon-germanium (SiGe), or combinations thereof.

4. The method of claim 3 , further comprising forming a top source/drain on the one or more vertical fins that spans the one or more vertical fins and covers a portion of the sacrificial top spacer fill.

5. The method of claim 4 , further comprising removing the sacrificial top spacer fill to form an upper void space, wherein the top source/drain bounds the upper void space on one side and the U-shaped trough bounds the upper void space on three sides.

6. The method of claim 4 , wherein the sacrificial top spacer fill is removed using an isotropic wet etch.