Semiconductor structure and fabrication method thereof

1. A semiconductor structure, comprising:

an insulation material layer having a top surface and a bottom surface;

a top semiconductor layer having a plurality of transistor regions formed on the top surface of the insulation material layer;

isolation structures formed in the top semiconductor layer between adjacent transistor regions;

a first dielectric layer formed over the top semiconductor layer;

a first heat-conducting layer, having a thermal conductivity higher than a thermal conductivity of the isolation structures, and passing through the insulation material layer, the isolation structure in the top semiconductor layer, and the first dielectric layer;

a second dielectric layer formed over the first dielectric layer;

an interconnect structure formed in the second dielectric layer; and

a bottom layer conductive via, passing through the first heat-conducting layer and a partial thickness of the second dielectric layer, and electrically connected with the interconnect structure.

2. The semiconductor structure according to claim 1 , further comprising:

gate structures formed on the top semiconductor layer in the transistor regions;

doping regions formed the in the top semiconductor layer at two sides of the gate structures;

zeroth conductive vias penetrating through the first dielectric layer formed on the doping regions;

zeroth conductive layers electrically connected with the zeroth conductive vias formed over the first dielectric layer; and

a carrier wafer bonded with a top surface of the second dielectric layer,

wherein the zeroth conductive layers are electrically connected with the zeroth conductive vias.

3. The semiconductor structure according to claim 1 , wherein the first heat-conducting layer is formed by:

forming a first opening passing through the insulation material layer, the top semiconductor layer and the first dielectric layer; and

filling the first opening with a first heat-conducting film.

4. The semiconductor structure according to claim 3 , wherein:

a width of the first opening is smaller than a distance between the adjacent transistor regions along a direction parallel to a surface of the top semiconductor layer.

5. The semiconductor structure according to claim 3 , wherein:

a width of the isolation structure between the first opening and an adjacent transistor region is in a range of approximately 0.1 μm-0.4 μm.

6. The semiconductor structure according to claim 1 , wherein:

the first heat-conducting layer is made of one of polysilicon and amorphous silicon.

7. The semiconductor structure according to claim 2 , further comprising:

a second heat-conducting layer with a thermal conductivity greater than a thermal conductivity of air formed on the bottom surface of the isolation material layer.

8. The semiconductor structure according to claim 7 , wherein:

the second heat-conducting layer is made of one of polysilicon and amorphous silicon.

9. The semiconductor structure according to claim 2 , wherein along a direction perpendicular to a top surface of the top semiconductor layer and directing from the insulation layer to the second dielectric layer, the interconnect structure comprises:

N (N≧2) layers of conductive layers; and

a plurality of N th conductive vias between (N−1) th conductive layers and N th conductive layers,

wherein:

the N th conductive vias electrically connect the (N−1) th conductive layers with the N th conductive layers.

10. The semiconductor structure according to claim 1 , further comprising:

a backside pad layer electrically connecting with the bottom layer conductive via formed over the insulation material layer.

11. A method for fabricating a semiconductor structure, comprising:

providing a bottom semiconductor layer, an insulation material layer on the bottom semiconductor layer and a top semiconductor layer having a plurality of transistor regions on the insulation material layer;

forming isolation structures between adjacent transistor regions in the top semiconductor layer;

forming gate structures on the top semiconductor layer in the transistor regions;

forming doping regions in the top semiconductor layer at two sides of the gate structures;

forming a first dielectric layer over the top semiconductor layer;

etching portions of the first dielectric layer, the top semiconductor layer and the insulation material layer between adjacent transistor regions until the bottom semiconductor layer is exposed to form a first opening;

forming a first heat-conducting layer having a thermal conductivity greater than a thermal conductivity of the isolation structure in the first opening; and

forming a bottom layer conductive via, passing through the first heat-conducting layer.

12. The method according to claim 11 , further comprising:

forming zeroth conductive vias passing through the first dielectric layer on surfaces of the doping regions;

forming zeroth conductive layers electrically connected with the zeroth conductive vias on a surface of the first dielectric layer;

forming a second dielectric layer over the first dielectric layer;

forming an interconnect structure having top conductive layers and electrically connected with the zeroth conductive layers in the second dielectric layer;

providing a carrier wafer;

bonding the carrier wafer with a top surface of the second dielectric layer and surfaces of the top conductive layers;

removing the bottom semiconductor layer;

etching the insulation material layer from a bottom surface to the top surface to form a through hole to connect with the interconnect structure, wherein

the bottom layer conductive via is formed in the through hole.

13. The method according to claim 11 , wherein:

the first heat-conducting layer is made of one of polysilicon and amorphous silicon.

14. The method according to claim 11 , wherein forming the first heat-conducting layer comprises:

forming a first heat-conducting film to fill the first opening and on a top surface of the first dielectric layer; and

removing the first heat-conducting film higher than the first dielectric layer.

15. The method according to claim 14 , before forming the heat-conducting film, further comprising:

forming a first stop layer on a bottom and side surfaces of the first opening and a top surface of the first dielectric layer; and

removing the first heat-conducting film above the first stop layer to form the first heat-conducting layer,

wherein:

the first stop layer is made of a material different from that of the first dielectric layer; and

the first stop layer is made of a material different from that of the first heat-conducting film.

16. The method according to claim 12 , before forming the through hole, further comprising:

forming a second heat-conducting layer on the bottom surface of the insulation material layer,

wherein:

a thermal conductivity of the second heat-conducting layer is greater than a thermal conductivity of air;

the through hole passes through the second heat-conducting layer; and

the second heat-conducting layer is made of one of polysilicon and amorphous silicon.

17. The method according to claim 12 , wherein:

a thermal conductivity of the bottom layer conductive via is greater than a thermal conductivity of the first heat-conducting layer.

18. The method according to claim 12 , wherein:

the through hole passes through the first heat-conducting layer and the isolation structure.

19. The method according to claim 18 , wherein:

a width of the first conducting layer at two sides of the through hole is greater than approximately 0.1 μm.

20. The method according to claim 12 , further comprising:

forming a backside pad layer electrically connected with the bottom layer conductive via over the bottom surface of the insulation material layer; and

forming a passivation layer over the bottom surface of the insulation material and portions of the backside pad layer.