Echo cancellation using minimal complexity in a device
Described herein are technologies related to an implementation of a system to measure and compensate non-linearity (e.g., echo cancellation) in a transceiver circuitry of a device. Particularly, the echo cancellation utilizes reduced number of components for power savings, and further increases efficiency of signal or data packet transmissions in the device. An echo signal is determined by sampling a power amplifier output signal. The output signal is split into signals with different delays. Down conversion and digital interpolation of the signal with the shortest delay is performed. An echo cancellation signal is calculated based on the output signal as received as an input signal to a receive chain. The calculated signal is subtracted from a received echo signal to generate an echo free signal.
1. A method of echo cancellation in a device, the method comprising:
determining an estimated echo signal, wherein the determining comprises:
sampling a power amplifier (PA) output signal;
splitting the sampled PA output signal into a plurality of signals with different delays;
choosing and down-converting a signal from the plurality of signals with a shortest delay by a down converter, wherein the down-converting of the plurality of signals is limited to the chosen signal with the shortest delay; and
performing digital interpolation on the down-converted signal with the shortest delay; and
calculating an echo cancelling signal from the PA output signal to an input of a receive chain, and
generating a second output signal by subtracting the calculated echo cancelling signal from a received echo signal.
2. The method as recited in claim 1 , wherein each delay of the different delays corresponds to an echo delay of signal leakage from a transmit chain to the receive chain.
3. The method as recited in claim 2 , wherein a number of each delay of the different delays is based upon a bandwidth (BW) of the PA output signal and delay spread of echoes of the device.
4. The method as recited in claim 1 , wherein the digital interpolation of the down-converted signal with the shortest delay provides longer delayed signals of output signals of the PA.
5. The method as recited in claim 1 further comprising:
converting the down-converted signal with the shortest delay into a digital signal prior to the interpolation.
6. The method as recited in claim 1 , wherein the calculating of the echo cancelling signal further comprises:
generating a digital weight (w) signal by operating on an adaptive algorithm;
complex multiplying between each delay of the different delays and a particular digital weight (w) signal that corresponds to each delay; and
combining products of the complex multiplications for each delay to generate the estimated echo signal.
7. The method as recited in claim 6 , wherein the digital weight (w) signal is based upon an output of the digital interpolation of the signal with the shortest delay and a down-converted signal from the receive chain.
8. The method as recited in claim 6 , wherein the adaptive algorithm utilizes a least mean square (LMS), a recursive least square (RLS), or a dichotomous coordinate descent (DCD) algorithm.
9. The method as recited in claim 6 , wherein the complex multiplication is implemented by a vector modulator.
10. The method as recited in claim 1 , wherein the down-converter is in addition to a second down-converter from the receive chain.
11. A device comprising:
a power amplifier (PA);
an echo canceller coupled to the PA and configured to generate an estimated echo signal, wherein the echo canceller comprises:
a finite impulse response (FIR) filter configured to generate signals with different delays from a sampled PA output signal;
a down-converter configured to down convert a signal with a shortest delay, the down-converting of the generated signals with different delays is limited to the signal with the shortest delay;
one or more interpolators configured to perform interpolation on the down-converted signal with the shortest delay; and
a receive chain configured to receive the estimated echo signal; and
a combiner to subtract the estimated echo signal from an actual echo signal to generate a second output signal.
12. The device as recited in claim 11 , wherein each delay on the different delays of the FIR filter corresponds to an echo delay of signal leakage from the PA output signal to the receiver chain.
13. The device as recited in claim 11 , wherein the down-converter is in coupled to a second down-converter from the receive chain to comprise a total of two down-converters to implement echo cancellation.
14. The device as recited in claim 11 further comprising a directional coupler configured to sample the PA output signal.
15. The device as recited in claim 11 further comprising:
a processor configured to perform an adaptive algorithm to generate a digital weight (w) signal;
a vector modulator configured to perform a complex multiplication between each delay of the different delays and a corresponding digital weight (w) signal; and
a combiner configured to add products of the complex multiplications from the vector modulators to generate the estimated echo signal.
16. The device as recited in claim 15 , wherein the digital weight (w) signal is based upon the an output of the digital interpolation of the signal with the shortest delay and a down-converted signal from the receiver chain.
17. The device as recited in claim 15 , wherein the adaptive algorithm utilizes a least mean square (LMS), a recursive least square (RLS), or a dichotomous coordinate descent (DCD) algorithm.
18. A device comprising:
a power amplifier (PA);
a directional coupler configured to sample an output of the PA; and
an echo canceller coupled to the directional coupler and the PA, wherein the echo canceller is configured to generate an estimated echo signal, wherein the echo canceller further comprises:
a finite impulse response (FIR) filter configured to generate signals with different delays based on the sampled PA output signal;
a down-converter configured to down convert a signal with a shortest delay from the generated signals with different delays, the down-converting of the generated signals with different delays is limited to the signal with the shortest delay;
interpolators configured to perform interpolation on the down-converted different delays;
a processor configured to perform an adaptive algorithm to generate a digital weight (w) signal;
a vector modulator configured to perform a complex multiplication between each delay of the different delays and a corresponding digital weight (w) signal; and
a combiner configured to add products of the complex multiplications from the vector modulators to generate the estimated echo signal; and
a receive chain configured to receive the estimated echo signal, wherein the estimated echo signal is subtracted from an actual echo signal to generate an echo-free signal.
19. The device as recited in claim 18 , wherein each delay on the generated different delays of the FIR filter corresponds to each echo delay of signal leakage from the PA output signal to the receiver chain.
20. The device as recited in claim 18 further comprising a low-noise amplifier (LNA) that is disabled when the residual echo signal is substantially high to avoid saturation in the LNA.