Hardware-based handling of missing interrupt propagation

1. A circuit, comprising:

one or more components to:

receive an interrupt associated with a device,

the interrupt relating to an event that needs attention, and

the interrupt being sent by the device via an interrupt line associated with the device;

send the interrupt associated with the device,

the interrupt being sent via an interrupt line associated with the circuit;

start a missing interrupt timer, associated with the interrupt, based on sending the interrupt,

the missing interrupt timer being associated with a threshold amount of time by which the interrupt is to be serviced;

identify, based on the missing interrupt timer, the interrupt as a missing interrupt; and

resend the missing interrupt via the interrupt line associated with the circuit, the missing interrupt being resent to cause the missing interrupt to be serviced.

2. The circuit of claim 1 , where the one or more components are associated with a level triggered interrupt stage included in an interrupt tree.

3. The circuit of claim 1 , where the one or more components, when sending the interrupt, are to send the interrupt to an edge triggered stage of an interrupt tree.

4. The circuit of claim 1 , where the one or more components, when starting the missing interrupt timer, are to:

wait a particular amount of time after sending the interrupt;

determine, after the particular amount of time, that the interrupt was not serviced within the particular amount of time; and

start the missing interrupt timer based on determining that the interrupt was not serviced within the particular amount of time.

5. The circuit of claim 1 , where the interrupt is one interrupt of a set of back-to-back interrupts sent by the device.

6. The circuit of claim 1 , where the one or more components, when identifying the interrupt as a missing interrupt, are to:

determine that the interrupt was not serviced within the threshold amount of time associated with the missing interrupt timer; and

identify the interrupt as a missing interrupt based on determining that the interrupt was not serviced within the threshold amount of time.

7. The circuit of claim 1 , where the one or more components implement debounce delay logic associated with delaying back-to-back interrupts sent by the device.

8. A method, comprising:

receiving, by a circuit, an interrupt associated with a device,

the interrupt being provided by the device,

the interrupt relating to an event that needs attention, and

the interrupt being received via a first interrupt line;

providing, by the circuit, the interrupt associated with the device,

the interrupt being provided via a second interrupt line;

initiating, by the circuit and after providing the interrupt, a timer associated with the interrupt,

the timer corresponding to a threshold amount of time by which the interrupt is to be serviced;

determining, by the circuit, that the interrupt is not serviced within the threshold amount of time;

identifying, by the circuit and based on determining that the interrupt was not serviced within the threshold amount of time, the interrupt as a missing interrupt; and

re-providing, by the circuit, the missing interrupt,

the missing interrupt being re-provided via the second interrupt line, and

the missing interrupt being re-provided to cause the missing interrupt to be received by a processor associated with servicing the missing interrupt.

9. The method of claim 8 , where the circuit is associated with an edge triggered interrupt stage included in an interrupt tree.

10. The method of claim 8 , where providing the interrupt comprises providing the interrupt to an edge triggered stage of an interrupt tree.

11. The method of claim 8 , further comprising:

waiting for a particular amount of time after providing the interrupt; and

initiating the timer after waiting for the particular amount of time after providing the interrupt.

12. The method of claim 8 , where the interrupt is one interrupt of a set of spurious interrupts provided by the device.

13. The method of claim 8 , where the threshold amount of time includes at least one of:

a user configured threshold amount of time;

a default threshold amount of time;

a static threshold amount of time; or

a dynamic threshold amount of time.

14. The method of claim 8 , where the circuit implements debounce delay logic associated with delaying one or more interrupts provided by the device.

15. A system, comprising:

one or more components associated with a stage of an interrupt tree to:

receive, via an interrupt line associated with a device, an interrupt sent by the device,

the interrupt relating to an event that needs attention;

send, via an interrupt line associated with the one or more components, the interrupt associated with the device,

the interrupt being sent to another stage of the interrupt tree;

determine that the interrupt was not serviced within a threshold amount of time after sending the interrupt;

identify, based on determining that the interrupt was not serviced within the threshold amount of time, the interrupt as a missing interrupt;

resend the missing interrupt via the interrupt line associated with one or more components,

the missing interrupt being resent to cause the missing interrupt to be serviced.

16. The system of claim 15 , where the other stage of the interrupt tree is an edge triggered stage of the interrupt tree.

17. The system of claim 15 , where the one or more components are further to:

wait a particular amount of time after sending the interrupt;

determine, after the particular amount of time, that the interrupt was not serviced within the particular amount of time; and

start a missing interrupt timer based on determining that the interrupt was not serviced within the particular amount of time,

the missing interrupt timer counting the threshold amount of time.

18. The system of claim 15 , where the interrupt is one interrupt of a set of back-to-back interrupts sent by the device.

19. The system of claim 15 , where the one or more components implement debounce delay logic associated with delaying interrupts sent by the device.

20. The system of claim 15 , where the one or more components, after resending the missing interrupt, are further to:

determine whether the resent interrupt was serviced within the threshold amount of time.