Solid state drive architectures

1. A solid state drive (SSD) comprising:

Dynamic Random Access Memory (DRAM);

flash memory;

an SSD controller; and

an interface to connect the SSD to a host having a Central Processing Unit (CPU) such that CPU exclusively reads data from, and writes to, the DRAM, the DRAM providing principal data storage during operation of the CPU;

the SSD controller to independently determine when to transfer data from the DRAM to the flash memory,

wherein, upon restart, the SSD controller to retrieve a stored snapshot of an operating state of the host at power down from the flash memory into the DRAM, comprising retrieving indexing data from a dump area of the flash memory and using the indexing data to load separate segments of the snapshot from the flash memory to the DRAM to restore a cleaned-up version of the snapshot in the DRAM for use by an operating system of the host.

2. A solid state drive (SSD) comprising:

Dynamic Random Access Memory (DRAM) configured to function as logical flash;

non-volatile flash memory to receive data from the DRAM;

a bus;

in which a Central Processing Unit of a host device reads and writes only to the DRAM and not the flash memory using the bus;

in which at least some writes to the drive are reported to the host device as stored in the non-volatile flash memory even though data from those writes is actually stored in the DRAM;

wherein, upon restart, the SSD to retrieve a stored snapshot of an operating state of the host device at power down from the flash memory into the DRAM, comprising retrieving indexing data from a dump area of the flash memory and using the indexing data to load separate segments of the snapshot from the flash memory to the DRAM to restore a cleaned-up version of the snapshot in the DRAM for use by an operating system of the host device.

3. The drive of claim 2 , in which the solid state drive writes data from the DRAM to the flash memory at predetermined points that are independent from commands issued by a system processor.

4. The drive of claim 2 , in which the DRAM simulates flash memory by storing files in the same way as NAND flash and responds to flash commands.

5. The drive of claim 4 , in which the DRAM simulates flash memory by using a FAT table or NTFS controls, updating logical records, combining files, and directly connecting to a SATA or PCI bus.

6. The drive of claim 1 , further comprising an energy storage device storing enough power to move data content stored in the DRAM to flash memory if external power to the solid state drive is interrupted.

7. The drive of claim 1 , in which the DRAM implements all read and write commands at full interface speed.

8. The drive of claim 1 , in which the DRAM stores program trace points and operation snapshots used by the SSD controller to minimize writes to the flash memory.

9. The drive of claim 1 , in which the solid state drive is configured to provide a full recovery of a last state of the host for any power down.

10. The drive of claim 1 , in which pages of the flash memory are individually identified as having errors and eliminated from a block while other pages in the block remain in use.

11. The drive of claim 10 , in which the flash memory comprises multi-level cell NAND flash, in which individually identifying pages as having errors and eliminating them from a block while other pages in the block remain in use increases the lifetime of the flash memory over flash memory that eliminates an entire block when an error is detected in a page within the block.

12. The drive of claim 1 , in which all data retained in the DRAM is written to the flash memory in response to a power down of the host.

13. The drive of claim 2 , further comprising high speed Direct Memory Access (DMA) for independent read and write operations to the DRAM.

14. The drive of claim 1 , further comprising a high speed internal bus, in which the DRAM and the flash memory are separately connected to the high speed internal bus, the flash memory being divided into separate modules, each module controlled by a different microprocessor configured to independently interface with the high speed internal bus.

15. The drive of claim 2 , in which the DRAM simulates flash memory storage by storing all the transfers to the flash memory and selectively holding the transfers to minimize write wear on the flash memory.

16. The drive of claim 1 , in which the SSD controller controls execution of a command by sending sub-commands to other microprocessors without the SSD controller directly managing data transfers, in which each microprocessor operates independently.

17. The drive of claim 2 , further comprising:

an internal bus operably connecting the DRAM and the flash memory; and

a master controller controlling data that sent over the internal bus between the DRAM and the flash memory.

18. The drive of claim 2 , further comprising multiple independent flash controllers each within a separate flash memory module such that the separate flash memory modules can be written in parallel.

19. The drive of claim 18 , in which each of the flash memory modules comprise:

a microprocessor;

flash memory;

memory buffers directly accessible to the microprocessor and flash memory;

an interface for writing data directly into the memory buffers; and

a buffer switch to switch the memory buffers between an external bus and an internal bus by transitioning to a null state.

20. The drive of claim 1 , wherein the DRAM is configured to operate in at least one of the following modes: logical record indexed data transfers and data transfers that are not indexed by logical records.

21. The drive of claim 2 , wherein the DRAM provides principal data storage during operation of the CPU wherein a portion of data written to the DRAM is not written to the flash memory.

22. A method for operation of a solid state drive (SSD) that comprises Dynamic Random Access Memory (DRAM) and a flash device comprising:

writing, by a Central Processing Unit (CPU) of a host device, to the solid state drive by sending commands and data to the DRAM, in which the DRAM is treated by the CPU as nonvolatile memory and as logical flash;

minimizing wear on the flash device by independently determining with an SSD controller when and whether to transfer data from the DRAM to the flash device;

in response to a loss of external power to the SSD, using a power system contained in the SSD to transfer data from the DRAM to the flash device; and

upon restart, retrieving a stored snapshot of an operating state of the host device at power down from the flash device into the DRAM, comprising retrieving indexing data from a dump area of the flash device and using the indexing data to load separate segments of the snapshot from the flash device to the DRAM to restore a cleaned-up version of the snapshot in the DRAM for use by an operating system of the host device.

23. The method of claim 22 , further comprising simulating flash memory by the DRAM logical flash by:

storing files in the same way as NAND flash in the DRAM logical flash; and

responding, with the DRAM logical flash, to flash commands.

24. The method of claim 23 , further comprising simulating flash memory by the DRAM logical flash by:

using a FAT table or NTFS data structure;

updating logical records;

combining files; and

directly connecting to a SATA or PCI bus.

25. The method of claim 22 , further comprising:

determining that a snapshot of a system state should be saved; and

saving the snapshot in a snapshot area of the DRAM logical flash using a dedicated file transfer route that does not use logical record numbers;

when solid state drive shuts down, saving at least one selected snapshot to the flash memory modules.

26. The method of claim 22 , further comprising reading data from the solid state flash device by:

receiving a read command from the CPU by a master controller in the solid state flash device;

determining, with the master controller, if files requested by the read command are stored in the DRAM logical flash;

if the files are stored in the DRAM logical flash, then transferring the files to the CPU.

27. The method of claim 22 , further comprising writing to the solid state flash device by:

sending, by the CPU, a write command and placing the data to be written on a system bus;

receiving, by the solid state flash device, the write command and accepting the data from the system bus;

storing the data on the DRAM logical flash; and

reporting to the CPU that the write to non-volatile memory is complete; and

further comprising, if the master controller determines that the data in the DRAM logical flash is not being used, then sending the data to the flash memory modules by:

sequentially enabling flash memory modules; and

transferring the data on an internal bus sequentially to enabled flash memory modules;

in which the data is striped over all of the flash memory modules to allow for parallel writes to the flash memory modules.

28. The method of claim 22 , further comprising a fast load operation comprising storing software executables on a protected area of the DRAM logical flash that is not accessible to the user.

29. The drive of claim 1 , wherein the DRAM comprises at least 8 Gigabytes of data storage.

30. The drive of claim 2 , wherein the DRAM comprises at least 8 Gigabytes of data storage.