IP Library Granted Patent US 9,950,921
Granted Patent B2
US 9,950,921 · App. 14/930,642 · Granted Apr 24, 2018

MEMS structure with improved shielding and method

Inventors: Te-Hsi “Terrence” Lee (San Jose, CA); Sudheer S. Sridharamurthy (Menlo Park, CA); Shingo Yoneoka (San Jose, CA); Wenhua Zhang (San Jose, CA)
Assignee: mCube Inc.
B81B7/0022B81B3/0086B81C1/00246B81C1/00801B81B2203/0118B81B2203/0307B81B2207/11B81C1/0038B81C1/00531B81C2201/053
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Quick Facts
Patent No.
US 9,950,921
App. No.
14/930,642
Granted
Apr 24, 2018
Kind
B2
Abstract

An integrated circuit includes a substrate member having a surface region and a CMOS IC layer overlying the surface region. The CMOS IC layer has at least one CMOS device. The integrated circuit also includes a bottom isolation layer overlying the CMOS IC layer, a shielding layer overlying a portion of the bottom isolation layer, and a top isolation layer overlying a portion of the bottom isolation layer. The bottom isolation layer includes an isolation region between the top isolation layer and the shielding layer. The integrated circuit also has a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer. The MEMS layer includes at least one MEMS structure having at least one movable structure and at least one anchored structure. The at least one anchored structure is coupled to a portion of the top isolation layer, and the at least one movable structure overlies the shielding layer.

Claims (23)

1. An integrated circuit comprising:

a substrate member having a surface region;

a CMOS IC layer overlying the surface region, the CMOS IC layer having a plurality of CMOS integrated circuits;

a bottom isolation layer made entirely of a first dielectric material overlying the CMOS IC layer;

a conductive shielding layer overlying a portion of the bottom isolation layer;

a top isolation layer made entirely of a second dielectric material disposed directly on a portion of the bottom isolation layer, wherein the bottom isolation layer comprises an isolation region between the top isolation layer and the conductive shielding layer, the isolation region extending to a sidewall of the top isolation region such that no conductive layer is adjacent to the sidewall of the top isolation region; and

a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer,

the MEMS layer including at least one MEMS structure having at least one movable structure and at least one anchored structure, the at least one movable structure being separated from the at least one anchored structure, wherein the at least one anchored structure is coupled to a portion of the top isolation layer, wherein the at least one movable structure overlies the shielding layer.

2. The integrated circuit of claim 1 wherein the shielding layer is disposed within a portion of the bottom isolation layer.

3. The integrated circuit of claim 1 wherein the shielding layer comprises a single-sided partial shielding layer underlying at least a portion of the movable structure.

4. The integrated circuit of claim 1 wherein the shielding layer comprises a full shielding layer underlying at least a portion of the movable structure and at least a portion of the anchored structure.

5. The integrated circuit of claim 4 wherein the isolation region is configured to separate the top isolation layer from the shielding layer.

6. The integrated circuit of claim 1 wherein the shielding layer comprises a polysilicon material or an aluminum material.

7. The integrated circuit of claim 1 wherein the shielding layer is underneath a gap between the at least one movable structure and at least one anchored structure.

8. The integrated circuit of claim 1 wherein the at least one MEMS structure comprises an accelerometer, a gyrometer, a magnetometer, or a pressure sensor.

9. An integrated circuit comprising: a substrate member having a surface region; a CMOS IC layer overlying the surface region, the CMOS IC layer having a plurality of CMOS integrated circuits; a bottom isolation layer made entirely of a first dielectric material overlying the CMOS IC layer; a shielding layer overlying a portion of the bottom isolation layer; a top isolation layer made entirely of a second dielectric material disposed directly on a portion of the bottom isolation layer, wherein the bottom isolation layer comprises an isolation region between the top isolation layer and the shielding layer, the isolation region being an exposed portion of the bottom isolation layer free from conductive contact with sidewall of the top isolation layer and the shielding layer; and a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer, the MEMS layer including at least one MEMS structure having at least one movable structure and at least one anchored structure, wherein the at least one anchored structure is coupled to a portion of the top isolation layer, wherein the at least one movable structure is separate from the at least one anchored structure and overlies the shielding layer.

10. The integrated circuit of claim 9 wherein the shielding layer is formed within a portion of the bottom isolation layer.

11. The integrated circuit of claim 9 wherein the shielding layer comprises a single-sided partial shielding layer underlying at least a portion of the movable structure.

12. The integrated circuit of claim 9 wherein the shielding layer comprises a full shielding layer underlying at least a portion of the movable structure and at least a portion of the anchored structure.

13. The integrated circuit of claim 12 wherein the isolation region is configured to separate the top isolation layer from the shielding layer.

14. The integrated circuit of claim 9 wherein the shielding layer comprises a polysilicon material or an aluminum material.

15. The integrated circuit of claim 9 wherein the shielding layer is underneath a gap between the at least one movable structure and at least one anchored structure.

16. The integrated circuit of claim 9 wherein the at least one MEMS structure comprises an accelerometer, a gyrometer, a magnetometer, or a pressure sensor.

Assignments (5)
PARTIAL TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 61948/0764 Recorded May 2, 2025
From: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS AGENT
To: MOVELLA INC.
Reel/Frame 071161/0930 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Nov 15, 2022
From: MOVELLA INC.
To: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS AGENT
Reel/Frame 061948/0764 →
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2022
From: SILICON VALLEY BANK
To: MOVELLA INC. (FORMERLY KNOWN AS MCUBE, INC.)
Reel/Frame 061763/0864 →
SECURITY INTEREST Recorded Mar 2, 2022
From: MOVELLA INC. (FKA MCUBE, INC.)
To: SILICON VALLEY BANK
Reel/Frame 059147/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2015
From: LEE, TE-HSI TERRENCE; SRIDHARAMURTHY, SUDHEER; YONEOKA, SHINGO; ZHANG, WENHUA
To: MCUBE INC.
Reel/Frame 037014/0170 →
Continuity (3)
Continuation 14302385 · Jun 11, 2014
Provisional Application 61835510 · Jun 14, 2013
Related Publication 20160052777A1 · Feb 25, 2016