Method to maintain power supply voltage during brownout

1. A method of maintaining a power supply voltage to a memory circuit, comprising:

storing a charge in a charge reservoir;

storing a charge on a power supply capacitor of the memory circuit;

receiving a power supply fail signal generated by a memory controller; and

applying charge from the charge reservoir to the power supply capacitor in response to the power supply fail signal.

2. A method as in claim 1 , wherein the charge reservoir is a capacitor.

3. A method as in claim 1 , wherein the power supply capacitor comprises a parallel plate capacitor having a dielectric.

4. A method as in claim 3 , wherein the dielectric comprises silicon dioxide.

5. A method as in claim 1 , wherein the power supply fail signal is a brownout signal that indicates a temporary power failure.

6. A method as in claim 1 , wherein applying charge comprises pumping charge from the charge reservoir through a pump capacitor.

7. A method of maintaining a power supply voltage to a memory circuit, comprising:

storing a separate charge on each of a plurality of capacitors;

storing a charge on a power supply capacitor of the memory circuit;

receiving a power supply fail signal generated by a memory controller;

receiving a control signal; and

sequentially applying charge from each capacitor of the plurality of capacitors to the power supply capacitor in response to the power supply fail signal and the control signal.

8. A method as in claim 7 , wherein each capacitor of the plurality of capacitors is a same size.

9. A method as in claim 7 , wherein each capacitor of the plurality of capacitors is a different size.

10. A method as in claim 7 , wherein the power supply fail signal is a brownout signal that indicates a temporary power failure.

11. A method as in claim 7 , wherein the control signal is a wordline enable signal.

12. A method as in claim 7 , wherein applying charge comprises pumping charge from each capacitor of the plurality of capacitors through a respective pump capacitor.

13. A power supply circuit, comprising:

a power supply terminal;

a power supply capacitor of a memory circuit;

a first transistor coupled between the power supply terminal and the power supply capacitor, the first transistor having a control terminal coupled to receive a power fail signal generated by a memory controller; and

a plurality of pump circuits coupled to the power supply capacitor, each pump circuit coupled to receive a respective first control signal and to apply charge to the power supply capacitor responsive to its respective first control signal; and

a plurality of control circuits, each control circuit coupled to a respective pump circuit, each control circuit arranged to produce the respective first control signal in response to a wordline enable signal and to the power fail signal.

14. A power supply circuit as in claim 13 , wherein each pump circuit comprises:

a respective reservoir capacitor; and

a respective pump capacitor coupled between the respective reservoir capacitor and the power supply capacitor.

15. A power supply circuit as in claim 13 , wherein at least one said respective second control signal is a delayed version of a previous said wordline enable signal.

16. A power supply circuit as in claim 13 , wherein each said wordline enable signal is an enable signal for a respective memory circuit in the memory circuit.