Switching regulator synchronous node snubber circuit
Various methods and devices that involve snubber circuits for switching power converters are disclosed. An example power converter has a snubbing circuit. The snubber circuit comprises a bypass capacitor connecting an input node of the power converter to a ground node of the power converter, a decoupling capacitor that connects the input node of the power converter to a snubber node, and a snubbing resistor that connects the snubber node to the ground node. The snubbing resistor connects the decoupling capacitor to the ground node of the power converter. The snubbing resistor is greater than 1 ohm. The decoupling capacitor is greater than 5 nanofarads and less than 0.5 microfarads. The bypass capacitor is greater than 1 microfarads.
1. A power converter with a snubber circuit, the snubber circuit comprising:
a first capacitor coupling an input node of the power converter to a ground node of the power converter;
a second capacitor having a first terminal, wherein the first terminal is coupled to the input node of the power converter;
a snubbing resistor coupling a second terminal of the second capacitor to the ground node;
a phase node;
a synchronous power transistor connected between the phase node and the ground node; and
a control power transistor connected between the input node and the phase node;
wherein the snubbing resistor is greater than 1 ohm;
wherein the first capacitor is greater than 1 microfarads;
wherein the second capacitor is greater than 5 nanofarads, and less than 0.5 microfarads; and
wherein the second capacitor comprises a capacitor multiplier and an integrated circuit capacitor, the capacitor multiplier multiplying a capacitance of the integrated circuit capacitor.
2. The power converter of claim 1 , further comprising:
an inductor connected to the phase node;
wherein the control power transistor, the inductor, and the synchronous power transistor are the only devices of the power converter that are connected to the phase node.
3. The power converter of claim 1 , wherein:
the capacitor multiplier comprises an amplifier, a first resistor having a first terminal and a second terminal, and a second resistor having a first terminal and a second terminal;
the first terminal of the first resistor is the first terminal of the second capacitor;
the second terminal of the first resistor is the second terminal of the second capacitor;
the first terminal of the first resistor is coupled to an output of the amplifier;
the second terminal of the first resistor is coupled to the first terminal of the second resistor;
an input of the amplifier and the second terminal of the second resistor are coupled to a first terminal of the integrated circuit capacitor; and
a second terminal of the integrated circuit capacitor is coupled to the ground node.
4. The power converter of claim 1 , wherein:
the capacitor multiplier comprises a transistor; and
the transistor of the capacitor multiplier is located in a package with one or both of the synchronous power transistor and the control power transistor.
5. The power converter of claim 1 , wherein:
the capacitor multiplier comprises a transistor; and
the transistor of the capacitor multiplier is located in a package with a transistor of a feedback circuit.
6. The power converter of claim 1 , wherein:
the capacitor multiplier comprises a transistor;
the transistor of the capacitor multiplier is formed on a substrate;
one or both of the control power transistor and the synchronous power transistor are also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.
7. The power converter of claim 1 , wherein:
the capacitor multiplier comprises a transistor;
the transistor of the capacitor multiplier is formed on a substrate;
a transistor of a feedback circuit is also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.
8. The power converter of claim 1 , wherein:
the snubbing resistor comprises a resistor emulator circuit.
9. The power converter of claim 8 , wherein the resistor emulator circuit comprises an integrated circuit based current mirror.
10. The power converter of claim 8 , wherein:
the resistor emulator circuit comprises a transistor; and
the transistor of the resistor emulator circuit is located in a package with one or both of the synchronous power transistor and the control power transistor.
11. The power converter of claim 8 , wherein:
the resistor emulator circuit comprises a transistor; and
the transistor of the resistor emulator circuit is located in a package with a transistor of a feedback circuit.
12. The power converter of claim 8 , wherein:
the resistor emulator circuit comprises a transistor;
the transistor of the resistor emulator circuit is formed on a substrate;
one or both of the synchronous power transistor and the control power transistor are also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.
13. The power converter of claim 8 , wherein:
the resistor emulator circuit comprises a transistor;
the transistor of the resistor emulator circuit is formed on a substrate;
a transistor of a feedback circuit is also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.
14. A method for damping oscillations on a phase node of a power converter comprising:
turning off a synchronous power transistor that is connected to the phase node and ground;
turning on a control power transistor to create a low impedance circuit path from an input node of the power converter to the phase node;
providing a first quantity of charge from a first capacitor to the phase node; and
providing a second quantity of charge from a second capacitor to the phase node;
wherein the first capacitor is greater than 1 microfarads and couples the input node to a ground node;
wherein the second capacitor is less than the first capacitor, greater than 5 nanofarads, and couples the input node to a resistor emulator circuit;
wherein the resistor emulator circuit emulates a resistance that is greater than 1 ohm and couples the second capacitor to the ground node; and
wherein the second quantity of charge is greater than the first quantity of charge.
15. The method of claim 14 , wherein the resistor emulator circuit comprises an integrated circuit based current mirror.
16. The method of claim 14 , wherein:
the resistor emulator circuit comprises a transistor; and
the transistor of the resistor emulator circuit is located in a package with one or both of the synchronous power transistor and the control power transistor.
17. The method of claim 14 , wherein:
the resistor emulator circuit comprises a transistor; and
the transistor of the resistor emulator circuit is located in a package with a transistor of a feedback circuit.
18. The method of claim 14 , wherein:
the resistor emulator circuit comprises a transistor;
the transistor of the resistor emulator circuit is formed on a substrate;
one or both of the synchronous power transistor and the control power transistor are also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.
19. The method of claim 14 , wherein:
the resistor emulator circuit comprises a transistor;
the transistor of the resistor emulator circuit is formed on a substrate;
a transistor of a feedback circuit is also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.
20. The method of claim 14 , wherein the second capacitor comprises a capacitor multiplier and an integrated circuit capacitor.
21. The method of claim 20 , wherein:
the capacitor multiplier comprises a transistor; and
the transistor of the capacitor multiplier is located in a package with one or both of the synchronous power transistor and the control power transistor.
22. The method of claim 20 , wherein:
the capacitor multiplier comprises a transistor; and
the transistor of the capacitor multiplier is located in a package with a transistor of a feedback circuit.
23. The method of claim 20 , wherein:
the capacitor multiplier comprises a transistor;
the transistor of the capacitor multiplier is formed on a substrate;
one or both of the synchronous power transistor and the control power transistor are also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.
24. The method of claim 20 , wherein:
the capacitor multiplier comprises a transistor;
the transistor of the capacitor multiplier is formed on a substrate;
a transistor of a feedback circuit is also formed on the substrate; and
the substrate is a substrate of a single integrated circuit.