Semiconductor package assembly

1. A semiconductor package assembly, comprising:

a first semiconductor package, comprising:

a first semiconductor die;

a first molding compound surrounding the first semiconductor die;

a first redistribution layer (RDL) structure disposed on a bottom surface of the first molding compound, wherein the first semiconductor die is coupled to the first RDL structure;

a second redistribution layer (RDL) structure disposed on a top surface of the first molding compound; and

a passive device physically contacting a top surface of the second RDL structure to directly electrically couple the passive device to the second RDL structure, wherein the passive device is coupled to the first semiconductor die without external conductive structures disposed outside of the first semiconductor package; and

a second semiconductor package stacked on the first semiconductor package and free from contact with the passive device, the second semiconductor package comprising:

a third redistribution layer (RDL) structure positioned such that the passive device is disposed between the second RDL structure and the third RDL structure; and

a second semiconductor die coupled to the second RDL structure.

2. The semiconductor package assembly as claimed in claim 1 , wherein the first semiconductor package comprises:

first conductive structures disposed on a first surface of the first RDL structure away from the first semiconductor die, wherein the first conductive structures are coupled to the first RDL structure.

3. The semiconductor package assembly as claimed in claim 2 , wherein the passive device is disposed on a first surface of the second RDL structure away from the first semiconductor die.

4. The semiconductor package assembly as claimed in claim 1 , wherein the passive device is free from being covered by the first molding compound.

5. The semiconductor package assembly as claimed in claim 3 , wherein the second RDL structure is coupled to the first RDL structure by first vias passing through the first molding compound between the first RDL structure and the second RDL structure.

6. The semiconductor package assembly as claimed in claim 5 , wherein the first semiconductor die is surrounded by the first vias.

7. The semiconductor package assembly as claimed in claim 5 , wherein two terminals of each of the first vias are respectively close to a second surface of the first RDL structure and a second surface of the second RDL structure, and wherein the second surface of the first RDL structure and the second surface of the second RDL structure are close to the first semiconductor die.

8. The semiconductor package assembly as claimed in claim 5 , further comprising:

a second molding compound surrounding the second semiconductor die, being in contact with the third RDL structure and the second semiconductor die.

9. The semiconductor package assembly as claimed in claim 8 , wherein the second RDL structure is disposed between the first RDL structure and the third RDL structure.

10. The semiconductor package assembly as claimed in claim 8 , wherein the second semiconductor package comprises:

second conductive structures disposed on a surface of the third RDL structure, which is away from the second semiconductor die, wherein the second conductive structures are coupled to the third RDL structure.

11. The semiconductor package assembly as claimed in claim 10 , wherein the passive device is surrounded by the second conductive structures.

12. The semiconductor package assembly as claimed in claim 8 , wherein the passive device is free from contact with the first molding compound.

13. The semiconductor package assembly as claimed in claim 8 , wherein the second semiconductor package is coupled to the first RDL structure by the second RDL structure and the first vias.

14. The semiconductor package assembly as claimed in claim 8 , wherein the first semiconductor die is a system-on-chip (SOC) die, and the second semiconductor die is a dynamic random access memory (DRAM) die.

15. The semiconductor package assembly as claimed in claim 14 , wherein the first semiconductor package is a system-on-chip (SOC) package, and the second semiconductor package is a DRAM package.

16. A semiconductor package assembly, comprising:

a first semiconductor package, comprising:

a first redistribution layer (RDL);

a second redistribution layer (RDL) structure on the first RDL structure;

a first molding compound having two opposite surfaces in contact with the first RDL structure and the second RDL structure, respectively; and

first vias passing through the first molding compound between the first RDL structure and the second RDL structure; and

a passive device in direct physical contact with a top surface of the second RDL structure to directly electrically couple the passive device to the second RDL structure, wherein the passive device is free from contact with the first molding compound, and wherein the passive device is coupled to the first semiconductor die without external conductive structures disposed outside of the first semiconductor package; and

a second semiconductor package stacked on the first semiconductor package and free from contact with the passive device, the second semiconductor package comprising:

a third redistribution layer (RDL) structure positioned such that the passive device is disposed between the second RDL structure and the third RDL structure; and

a dynamic random access memory (DRAM) die coupled to the second RDL structure.

17. The semiconductor package assembly as claimed in claim 16 , further comprising:

a system-on-chip (SOC) die coupled to the first RDL structure and surrounded by the first molding compound and the first vias.

18. The semiconductor package assembly as claimed in claim 17 , wherein the system-on-chip (SOC) die is coupled to a surface of the first RDL structure, which is close to the system-on-chip (SOC) die.

19. The semiconductor package assembly as claimed in claim 17 , wherein the passive device is in contact with a surface of the second RDL structure, which is away from the system-on-chip (SOC) die.

20. The semiconductor package assembly as claimed in claim 17 , wherein the first semiconductor package comprises:

first conductive structures disposed on a surface of the first RDL structure, which is away from the system-on-chip (SOC) die, wherein the first conductive structures are coupled to the first RDL structure.

21. The semiconductor package assembly as claimed in claim 16 , wherein the first vias are coupled to the first RDL structure and the second RDL structure.

22. The semiconductor package assembly as claimed in claim 16 , further comprising:

a second molding compound surrounding the DRAM die, being in contact with the third RDL structure and the DRAM die; and

second conductive structures disposed on a surface of the third RDL structure, which is away from the DRAM die, wherein the second conductive structures are coupled to the third RDL structure.

23. The semiconductor package assembly as claimed in claim 22 , wherein the second RDL structure is disposed between the first RDL structure and the third RDL structure.

24. The semiconductor package assembly as claimed in claim 22 , wherein the passive device is surrounded by the second conductive structures and free from contact with the second semiconductor package.

25. A semiconductor package assembly, comprising:

a first semiconductor package, comprising:

a first molding compound having two opposite surfaces;

a first redistribution layer (RDL) and a second redistribution layer (RDL) structure on the two opposite surfaces; and

first conductive structures in contact with the first RDL structure and free from contact with the first molding compound; and

a passive device in direct physical contact with a top surface of the second RDL structure to directly electrically couple the passive device to the second RDL structure, wherein the passive device is free from contact with the first molding compound, and wherein the passive device is coupled to the first semiconductor die without external conductive structures disposed outside of the first semiconductor package; and

a second semiconductor package stacked on the first semiconductor package and free from contact with the passive device, the second semiconductor package comprising:

a third redistribution layer (RDL) structure positioned such that the passive device is disposed between the second RDL structure and the third RDL structure; and

a dynamic random access memory (DRAM) die coupled to the second RDL structure.

26. The semiconductor package assembly as claimed in claim 25 , further comprising:

a system-on-chip (SOC) die being coupled to the first RDL structure and surrounded by the first molding compound and first vias, wherein the first vias pass through the first molding compound between the first RDL structure and the second RDL structure.

27. The semiconductor package assembly as claimed in claim 26 , wherein the first vias are coupled to the first RDL structure and the second RDL structure.

28. The semiconductor package assembly as claimed in claim 25 , further comprising:

a second molding compound surrounding the DRAM die, being in contact with the third RDL structure and the DRAM die; and

second conductive structures disposed on a surface of the third RDL structure, which is away from the DRAM die, wherein the second conductive structures are coupled to the third RDL structure.

29. The semiconductor package assembly as claimed in claim 28 , wherein the second RDL structure is disposed between the first RDL structure and the third RDL structure.

30. The semiconductor package assembly as claimed in claim 29 , wherein the passive device is surrounded by the second conductive structures and is free from contact with the second semiconductor package.