IP Library Granted Patent US 9,979,277
Granted Patent B2
US 9,979,277 · App. 15/450,901 · Granted May 22, 2018

PWM control device and three-level power conversion device using PWM control device

Inventor: Taku Takaku (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H02M1/38H02M7/483H02M7/5395
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Quick Facts
Patent No.
US 9,979,277
App. No.
15/450,901
Granted
May 22, 2018
Kind
B2
Abstract

A pulse width modulation (PWM) control device for converting a first PWM signal for a two-level power conversion device to a second PWM signal for a three-level power conversion device, the three-level power conversion device including a switch, the second PWM signal driving the switch through a drive unit. The PWM control device includes an input terminal for receiving the first PWM signal for the two-level power conversion device, a conversion unit configured to convert the first PWM signal into the second PWM signal for the three-level power conversion device, and an output unit that outputs the second PWM signal to the drive unit.

Claims (50)

1. A pulse width modulation (PWM) control device for converting a first PWM signal for a two-level power conversion device to a second PWM signal for a three-level power conversion device, the three-level power conversion device including a switch that is drivable by the second PWM signal through a drive unit, the PWM control device comprising:

an input terminal for receiving the first PWM signal for the two-level power conversion device;

a conversion unit configured to convert the first PWM signal into the second PWM signal for the three-level power conversion device, the conversion unit including

a low pass filter that filters the first PWM signal and extracts a fundamental wave of the first PWM signal,

a frequency divider circuit that binarizes the fundamental wave, and halves a frequency of the fundamental wave, and

a delay circuit that shifts a phase of the fundamental wave; and

an output unit that outputs the second PWM signal to the drive unit.

2. The PWM control device according to claim 1 , wherein the output unit includes:

an AND circuit that performs an AND operation on an output signal of the delay circuit and the first PWM signal; and

a branching circuit, which includes a NOT circuit that inverts an output signal of the AND circuit.

3. The PWM control device according to claim 2 , wherein

the drive unit further includes a first drive unit and a second drive unit, and

the branching circuit is configured to output the output signal of the AND circuit and an output signal of the NOT circuit respectively to the first and second drive units.

4. A three-level power conversion device that receives a pulse width modulation (PWM) signal for a two-level power conversion device, comprising:

a main circuit, including four semiconductor switches that form an upper arm and a lower arm;

four drive units for respectively driving the four semiconductor switches; and

first and second PWM control devices, each including

an input terminal for receiving the PWM signal for the two-level power conversion device,

a conversion unit, and

an output unit, wherein

the conversion unit converts the received PWM signal into a first PWM signal for the three-level power conversion device and a second PWM signal for the three-level power conversion device, which are outputted to the four drive units via the output units, and

the conversion unit includes

a low pass filter that filters the received PWM signal and extracts a fundamental wave of the received PWM signal;

a frequency divider circuit that binarizes the fundamental wave, and halves a frequency of the fundamental wave; and

a delay circuit that shifts a phase of the fundamental wave.

5. The three-level power conversion device according to claim 4 , wherein

the main circuit has an intermediate-level input terminal and a terminal that connects the upper arm and the lower arm,

two of the four semiconductor switches are reverse blocking switches, which are connected in series or in parallel in an opposite direction between the intermediate-level input terminal and the terminal that connects the upper arm and the lower arm, and

the two reverse blocking switches receive the first and second PWM signals outputted from the output units of the first and second PWM control devices, respectively.

6. A power conversion device, comprising:

three of the three-level power conversion device of claim 4 , wherein

the delay circuits in the three-level power conversion devices have such different delay amounts that phases of output signals of the three three-level power conversion devices are different from one another by 120 degrees.

7. A three-level power conversion device that receives a pulse width modulation (PWM) signal for a two-level power conversion device, comprising:

a main circuit, including four semiconductor switches that form an upper arm and a lower arm;

four drive units for respectively driving the four semiconductor switches; and

a PWM control device, including

an input terminal for receiving the PWM signal for the two-level power conversion device,

a conversion unit, including a delay circuit, configured to convert the received PWM signal into another PWM signal for the three-level power conversion device,

a first AND circuit configured to perform an AND operation on an output signal of the delay circuit and the received PWM signal,

a second AND circuit configured to perform an AND operation on an inverted signal of the output signal of the delay circuit and the received PWM signal,

a first branching circuit, which includes a first NOT circuit that inverts an output signal of the first AND circuit, and

a second branching circuit, which includes a second NOT circuit that inverts an output signal of the second AND circuit; wherein

the first branching circuit and the second branching circuit generate four output signals, which are inputted to the four semiconductor switches respectively via the four drive units.

8. The three-level power conversion device according to claim 7 , wherein

the main circuit has an intermediate-level input terminal and a terminal that connects the upper and lower arms,

two of the four semiconductor switches are reverse blocking switches, which are connected in series or in parallel in an opposite direction between the intermediate-level input terminal and the terminal that connects the upper and lower arms, and

two of the four output signals of the first and second branching circuits are inputted respectively to the two reverse blocking switches.

9. A power conversion device, comprising:

three of the three-level power conversion device of claim 7 , wherein

the delay circuits in the three-level power conversion devices have such different delay amounts that phases of output signals of the three three-level power conversion devices are different from one another by 120 degrees.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2017
From: TAKAKU, TAKU
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 041477/0267 →
Priority Claims (1)
JP 2016-054144 · Mar 17, 2016 · national
Continuity (1)
Related Publication 20170271995A1 · Sep 21, 2017