IP Library Granted Patent US 9,987,721
Granted Patent B2
US 9,987,721 · App. 14/421,578 · Granted Jun 5, 2018

Double-side polishing method

Inventors: Masanao Sasaki (Nishigo-mura, JP); Kazuaki Aoki (Nishigo-mura, JP); Taichi Yasuda (Tokyo, JP); Taketoshi Sato (Takasaki, JP); Takehiro Yuasa (Takasaki, JP); Kazumasa Asai (Nagano, JP); Daisuke Furukawa (Suzaka, JP)
B24B37/28B24B37/08H01L21/02024H01L21/304
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Quick Facts
Patent No.
US 9,987,721
App. No.
14/421,578
Granted
Jun 5, 2018
Kind
B2
Abstract

A double-side polishing method of polishing both surfaces of a wafer by holding the wafer with a carrier including a holding hole configured to hold the wafer and a ring-shaped resin insert disposed along an internal circumference of the holding hole, the resin insert having an inner circumferential surface configured to contact a peripheral portion of the wafer, interposing the carrier between upper and lower turn tables to which polishing pads are attached, polishing both the surfaces of the wafer while maintaining planarity of the inner circumferential surface at or below 100 μm and verticalness of the inner circumferential surface at or below 5°. The method can inhibit the degradation of the flatness of the polished wafer, such as particularly an outer circumferential sag, due to variation in shape of the inner circumferential surface of the resin insert of a carrier.

Claims (13)

1. A double-side polishing method of simultaneously polishing both surfaces of a wafer by holding the wafer with a carrier including a holding hole configured to hold the wafer and a ring-shaped resin insert disposed along an internal circumference of the holding hole, the resin insert having an inner circumferential surface configured to contact a peripheral portion of the wafer to be held, and interposing the carrier between upper and lower turn tables to which polishing pads are attached, the method comprising:

polishing both the surfaces of the wafer while maintaining planarity of the inner circumferential surface at or below 100 μm and verticalness of the inner circumferential surface at or below 5°, where the planarity is defined by the maximum difference in elevation of irregularities of the inner circumferential surface of the resin insert, and the verticalness is defined by an angle formed between a straight line perpendicular to a main surface of the carrier and a straight line joining an upper edge portion and a lower edge portion of the inner circumferential surface.

2. The double-side polishing method according to claim 1 , wherein after polishing both the surface of the wafer, the inner circumferential surface of the resin insert is ground or cut to maintain the planarity and the verticalness.

3. The double-side polishing method according to claim 1 , wherein both the surfaces of the wafer are polished while the planarity is maintained at or below 25 μm and the verticalness is maintained at or below 2°.

4. The double-side polishing method according to claim 2 , wherein both the surfaces of the wafer are polished while the planarity is maintained at or below 25 μm and the verticalness is maintained at or below 2°.

5. The double-side polishing method according to claim 1 , wherein the upper and lower turn tables interpose a plurality of the carriers therebetween to simultaneously polish both surfaces of a plurality of the wafers.

6. The double-side polishing method according to claim 2 , wherein the upper and lower turn tables interpose a plurality of the carriers therebetween to simultaneously polish both surfaces of a plurality of the wafers.

7. The double-side polishing method according to claim 3 , wherein the upper and lower turn tables interpose a plurality of the carriers therebetween to simultaneously polish both surfaces of a plurality of the wafers.

8. The double-side polishing method according to claim 4 , wherein the upper and lower turn tables interpose a plurality of the carriers therebetween to simultaneously polish both surfaces of a plurality of the wafers.

9. The double-side polishing method according to claim 5 , wherein both the surfaces of the wafers are polished while a difference in inner diameter among the respective resin inserts of the plurality of the carriers is maintained at or below 0.5 mm.

10. The double-side polishing method according to claim 6 , wherein both the surfaces of the wafers are polished while a difference in inner diameter among the respective resin inserts of the plurality of the carriers is maintained at or below 0.5 mm.

11. The double-side polishing method according to claim 7 , wherein both the surfaces of the wafers are polished while a difference in inner diameter among the respective resin inserts of the plurality of the carriers is maintained at or below 0.5 mm.

12. The double-side polishing method according to claim 8 , wherein both the surfaces of the wafers are polished while a difference in inner diameter among the respective resin inserts of the plurality of the carriers is maintained at or below 0.5 mm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2015
From: SASAKI, MASANAO; AOKI, KAZUAKI; YASUDA, TAICHI; SATO, TAKETOSHI; YUASA, TAKEHIRO; ASAI, KAZUMASA; FURUKAWA, DAISUKE
To: SHIN-ETSU HANDOTAI CO., LTD.
Reel/Frame 034959/0395 →
Priority Claims (1)
JP 2012-196642 · Sep 6, 2012 · national
Continuity (1)
Related Publication 20150217425A1 · Aug 6, 2015